VCO for wide tuning, low phase noise frequency synthesizer

[litw]

Dear all, It's happy to see there's such a group. I need to design an
integrated frequency syntheizer with phase noise lower than 80dbc/Hz at
20kHz offset and a tuning range of one decade, say 90-900MHz. I need to
choose between LC vco and ring vcos.

LC VCO may provide a better phase noise but its tuning range is very
limited. A ring oscillator would provide a wider range but its phase
noise is somewhere 20-30dB above the LC outputs. I'd like to see how do
you guys think about this.

My plan would be a bank of LC's to cover an octave of range, and use /2
blocks to generate the frequncies blow. But that costs a lot of chip
area with spiral inductors (at least 4). Another maybe a ring
oscillator with a wide loop bandwidth but for a certain frequency
resolution that requires a fractional-N loop divider which increase
greatly the digital complexity. I am basically an analog guy I don't
like to mess up with too much digital stuff.

Just my ideas. I'd like to see how you guys would think. Thanks for looking.

litw

 

[Richard Hosking]

Look at > http://www.qsl.net/ke5fx/synth.html
for a design to cover 1000-2000 MHz and then mix this down to 90 to 900
MHz with a oscillator on 900 MHz (LPF to remove the LO might be an issue
) The phase noise for this was about -87dBc at 10 KHz from memory.
The software is largely written to drive it though this would need some work

Richard

 

[Robert Lacoste]

Rather than a bank of multipliers, why aren't you using a 1.09-1.9GHz
wideband VCO, mixed with a fixed 1GHz signal and low-pass filtered to get a
90 to 900MHz signal ? You will need two oscillators but the phase noise of
the fixed one can be very low. For the 1.09 to 1.9GHz you could use for
example a Minicircuits ROS2150VW, its phase noise is -96dBc/Hz at 10KHz

Cheers,

Robert Lacoste - ALCIOM : The mixed signals experts
http://www.alciom.com

 

[Mike]

Dear all, It's happy to see there's such a group. I need to design an
integrated frequency syntheizer with phase noise lower than 80dbc/Hz at
20kHz offset and a tuning range of one decade, say 90-900MHz. I need to
choose between LC vco and ring vcos.

LC VCO may provide a better phase noise but its tuning range is very
limited. A ring oscillator would provide a wider range but its phase
noise is somewhere 20-30dB above the LC outputs. I'd like to see how do
you guys think about this.

In a modern CMOS process (0.18u or better), you can exceed -90dBc/Hz at
10kHz offset with a ring oscillator in a well designed PLL. The ring
oscillator tuning range is limited by the supply range, and it's difficult
to get a factor of 2 simply from changing the VCO supply. Modifying the VCO
architecture to increase the tuning range will probably cost you some
noise, but there is some margin to work with.

If you're designing in CMOS, pick up a copy of Hajimiri's book or track
down his papers on low noise CMOS ring oscillators. He concentrates on
jitter more than phase noise, and even though the two are related, jitter
is related to the integral of phase noise power spectrum, so you can get
low jitter even with high phase noise, as long as the noise bandwidth isn't
too large.

-- Mike --

 

[John Larkin]

Dear all, It's happy to see there's such a group. I need to design an
integrated frequency syntheizer with phase noise lower than 80dbc/Hz at
20kHz offset and a tuning range of one decade, say 90-900MHz. I need to
choose between LC vco and ring vcos.

LC VCO may provide a better phase noise but its tuning range is very
limited. A ring oscillator would provide a wider range but its phase
noise is somewhere 20-30dB above the LC outputs. I'd like to see how do
you guys think about this.

My plan would be a bank of LC's to cover an octave of range, and use /2
blocks to generate the frequncies blow. But that costs a lot of chip
area with spiral inductors (at least 4). Another maybe a ring
oscillator with a wide loop bandwidth but for a certain frequency
resolution that requires a fractional-N loop divider which increase
greatly the digital complexity. I am basically an analog guy I don't
like to mess up with too much digital stuff.

Just my ideas. I'd like to see how you guys would think. Thanks for looking.

litw

I'm working on a similar problem... how to generate an accurate,
low-jitter clock from DC to maybe 2 GHz. I was thinking of using a
cheap commercial octave-bandwidth 1-2 GHz VCO and a binary divider
chain to span 2 GHz down to 10 MHz. The chain would be phase locked to
a 0-10 MHz DDS source; below 10 MHz, I'd just use the DDS itself.

Something like that.


We could have an interesting discussion on DDS lowpass filters.

John

 

[Jim Thompson]

I'm working on a similar problem... how to generate an accurate,
low-jitter clock from DC to maybe 2 GHz. I was thinking of using a
cheap commercial octave-bandwidth 1-2 GHz VCO and a binary divider
chain to span 2 GHz down to 10 MHz. The chain would be phase locked to
a 0-10 MHz DDS source; below 10 MHz, I'd just use the DDS itself.

Something like that.


We could have an interesting discussion on DDS lowpass filters.

John

Hmmm! Wonder how a ring would do for 924MHz to 1188MHz?

...Jim Thompson

 

[John Larkin]

Hmmm! Wonder how a ring would do for 924MHz to 1188MHz?

...Jim Thompson

Doesn't a ring oscillator frequency depend a lot on Vcc? That would
require ppm-level Vcc quiet to deliver ppm-level FM or jitter
performance.

John

 

[Winfield Hill]

John Larkin wrote...

Doesn't a ring oscillator frequency depend a lot on Vcc?
That would require ppm-level Vcc quiet to deliver ppm-level
FM or jitter performance.

It depends on the local servo-generated voltage applied to
the ring oscillator inverters. Ideally the noise on this
voltage can be quite low, not much more than the voltage
noise of the servo integrator opamp. Some extra circuitry
(cascode stages, etc.) may be required to insure high PSRR.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Jim Thompson]

Doesn't a ring oscillator frequency depend a lot on Vcc? That would
require ppm-level Vcc quiet to deliver ppm-level FM or jitter
performance.

John

I've done *bipolar* ring VCO's in the past that were
current-controlled (GPS application, where noise isn't so critical,
since it's a "correlation" receiver).

I've sent them an E-mail to see what kind of noise performance they
measured.

...Jim Thompson

 

[litw]

Thank you Richard, It's a very versatile and convienent circuit in the
link. I am actually designing part of an integrated TV tuner chip so I
may need one like this in the testing in case mine does not work.
Another issue i didn't mention is that I need to generate precise
quadrature outputs for image rejection. I believe DDS can make precise
quadratures but I am not sure how to make this happen at the 90-900M range.

regards
litw

 

[litw]

Thank you very much Robert, However I am on TSMC.35 cmos and am supposed
to do this all on chip. I can design a 1.1-2GHz wideband but it will be
a ring oscillator. I am not quite sure about its noise performance even
I put it in a PLL with say 5MHz of loop bandwidth, which requires a
complex fractional-N loop divider for the resolution, it may also be
sigma-delta to remove the spurs associated. I mean I can do it but i'd
like to explore some new ideas as suggested by my boss
Another issure, two oscillators may talk to each other secretly that we
cannot control. In this case say if I want a 90M, the first oscillates
at 1.09G amd the other one at 1G. I don't know how the realistic would
be. I guess current simulators do not know how to find the coupling
between these two on chip.
best
litw

 

[litw]

Hi Mike,
Unfortunately I am working on TSMC.35, which has neither good
inductor or good ring oscillator It even does not have an inductor
model. I have to manually use Asitic to calculate the inductance i draw.

I saw some of Hajimiri's paper however under this technology the
improments I can make is very limited too. I suppose you are referring
his paper on June 1999 JSSC. I am trying to understand... It's pretty long.

In the spectre when i work with a PLL, if i want to find the output
phase noise, I have no good methods. the PSS won't work since the PLL is
not a periodic. Recenly they provided QPSS but it has no documentation
at all. I may be able to find the jitter from *very* precise therefore
slow transient simulations and try to convert to phase noise, but
according to your comments, they are not directed related. So how did
you guys simulate the performance of a PLL, besides using macromodel
level approach?

best
litw

 

[litw]

Jim,
why not an LC? This freqency range is easy to cover with even a PMOS
varactor.
litw

 

[litw]

John,
DDS low pass filter, I have no experience but I guess it needs to filter
out the quantization noise which is white and depends on the resolution
of the DAC. What's the challenge you face in this part? I am interested.
litw

 

[litw]

Do you mean a current-starving ring oscillator? Invertors are hooked to
current sources instead of directly VCC and gnd?
litw

 

[Jim Thompson]

Do you mean a current-starving ring oscillator? Invertors are hooked to
current sources instead of directly VCC and gnd?
litw

PECL (bipolar)

...Jim Thompson

 

[Mike]

Hi Mike,
Unfortunately I am working on TSMC.35, which has neither good
inductor or good ring oscillator It even does not have an inductor
model. I have to manually use Asitic to calculate the inductance i draw.

I saw some of Hajimiri's paper however under this technology the
improments I can make is very limited too. I suppose you are referring
his paper on June 1999 JSSC. I am trying to understand... It's pretty long.

In the spectre when i work with a PLL, if i want to find the output
phase noise, I have no good methods. the PSS won't work since the PLL is
not a periodic. Recenly they provided QPSS but it has no documentation
at all. I may be able to find the jitter from *very* precise therefore
slow transient simulations and try to convert to phase noise, but
according to your comments, they are not directed related. So how did
you guys simulate the performance of a PLL, besides using macromodel
level approach?

I find the jitter of my VCO using a slow transient simulation. Since it's
only the VCO, the simulation goes much faster than a full PLL. Then, I plug
that result into a mathematical model, along with the other noise sources,
to estimate the jitter of the closed loop PLL. McNeill, "Jitter in Ring
Oscillators," JSSC, 1997, provides a basic model.

I said that jitter is related to the integral of phase noise, not that they
aren't directly related. In fact, they are directly related, but if the
only thing you know is the total jitter of your PLL, there's no way to
reliably reconstruct the power spectrum.

-- Mike --

 

[John Miles]

Dear all, It's happy to see there's such a group. I need to design an
integrated frequency syntheizer with phase noise lower than 80dbc/Hz at
20kHz offset and a tuning range of one decade, say 90-900MHz. I need to
choose between LC vco and ring vcos.

LC VCO may provide a better phase noise but its tuning range is very
limited. A ring oscillator would provide a wider range but its phase
noise is somewhere 20-30dB above the LC outputs. I'd like to see how do
you guys think about this.

My plan would be a bank of LC's to cover an octave of range, and use /2
blocks to generate the frequncies blow. But that costs a lot of chip
area with spiral inductors (at least 4). Another maybe a ring
oscillator with a wide loop bandwidth but for a certain frequency
resolution that requires a fractional-N loop divider which increase
greatly the digital complexity. I am basically an analog guy I don't
like to mess up with too much digital stuff.

Just my ideas. I'd like to see how you guys would think. Thanks for looking.

Your phase-noise spec isn't very aggressive, so the easiest solution for
you will be to generate your tunable signal at, say, 1-2 GHz, and mix it
with a fixed source at 2 GHz to get your DC-1 Ghz output range. I would
not monkey around with a bank of subband oscillators and filters unless
I needed much better noise performance than you do.

(You could mix with a 1 GHz source, if you don't mind the 1 GHz source
bleeding through into your output signal. It will be difficult to
eliminate a 1 GHz internal signal from the output of a synthesizer that
needs to cover 900 MHz. A 2 GHz source will put your unwanted mixing
product in the 3-4 GHz range, which is trivial to filter out, at the
cost of a few dB of noise.)

A suitable main VCO would be the Mini-Circuits ROS-2150VW (970-2150 MHz
coverage, around US $30.00 each in small quantities). Your fixed 2 GHz
source could use an ROS-2000 (rated at -100 dBc/Hz at 10 kHz offsets).
At $10, the MCA1-42MH looks like a good candidate for the mixer.

You don't say what tuning step size you need, but the hybrid synthesizer
project at http://www.qsl.net/ke5fx/synth.html will give you 1-Hz
precision between 1 and 2 GHz. Mix that with a 2-GHz synthesizer and
you have a very handy DC-1 GHz source.

-- jm

 

[John Miles]

Your phase-noise spec isn't very aggressive, so the easiest solution for
you will be to generate your tunable signal at, say, 1-2 GHz, and mix it
with a fixed source at 2 GHz to get your DC-1 Ghz output range.

Sorry, I didn't see all the other replies due to a glitch in the foul
Matrix that is my newsreader. Never mind, please disregard.

-- jm