up counter need help

[vead]

table for 3 bit up counter

present state next state
N A B C
0 0 0 0 0 0 1
1 0 0 1 0 1 0
2 0 1 0 0 1 1
3 0 1 1 1 0 0
4 1 0 0 1 0 1
5 1 0 1 1 1 0
6 1 1 0 1 1 1
7 1 1 1 0 0 0

present state I think present state means this
N A B C
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0

next state means

N A B C
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
0 0 0 0


that's circuit is very complex for me don't know any idea what i do next
1)how to find out input for counter
2)how to find out output for counter

 

[Harald Kapp]

a) N= number of the state in decimal, not required for the logic.

b) Input and output are given:
output = present state
input = next state
Plus a clock to make it count.

The counter has three flipflops: A, B and C with associated states 000, 001, 010 etc.
Input tho the counter is the current state and a clock. The logic needs to find the nect state from the current state. The clock will then enter the new state into the flipflops with the active clock edge.

Example:
Current state: A=00, B=0, C=0 (000). next state: A=0, B=0, C=1 (001)
Find the logic that creates output 001 from input 000. The output of this logic is input to the D-input of the flipflops. The flipflops will change from 000 to 001 with the next clock.
Repeat for the other states. minimize the resulting logic to use few gates.

Tip: use a Karnaughh diagram to minimize the logic.

 

[vead]

a) N= number of the state in decimal, not required for the logic.

b) Input and output are given:
output = present state
input = next state
Plus a clock to make it count.

The counter has three flipflops: A, B and C with associated states 000, 001, 010 etc.
Input tho the counter is the current state and a clock. The logic needs to find the nect state from the current state. The clock will then enter the new state into the flipflops with the active clock edge.

Example:
Current state: A=00, B=0, C=0 (000). next state: A=0, B=0, C=1 (001)
Find the logic that creates output 001 from input 000. The output of this logic is input to the D-input of the flipflops. The flipflops will change from 000 to 001 with the next clock.
Repeat for the other states. minimize the resulting logic to use few gates.

Tip: use a Karnaughh diagram to minimize the logic.

I try k map for D0 flip flop
A B C D0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
0 0 0 1

K map

A/BC 00 01 11 10

1 0 0 0
1 1 1 1

I am not sure that I am correct

how to find out output D0 (equations)

 

[mursal]

You need to use a flip-flop to divide the clock input by 2. 3 flip flips will give you a binary count 0 to 7 (000 - 111). Click

Hope this helps, good luck

 

[Harald Kapp]

Mursal linked you to an asnchronous counter. That is one possible solution.
I tipped you to a synchronous counter. That is another solution.

Both realizations have advantages and disadvantages. From what you gave us in your original post, both realizations will lead to a valid result.


For the synchronous counter:
Your attempt at a K-map I do not understand. You have three inputs A,B and C You will need three outputs A', B' and C' which represent the next state and will be latched into the flipflops with the next clock. A single output D0 of the logic will lead to no result.

Read this tutorial on the design of synchronous counters.

By the way, I'm quite sure this is homework, so I will move this thread in the relevant section.