Hi All,
I know this is probably a rather trivial question / circuit for most
people in this group, but since I'm having a hard time visualizing
exactly what is going on in the circuit I was hoping someone here
might not mind giving me some additional insight into what is going
on.
The circuit is the 2 transistor Pulse Generator from Forrest Mim's
Electronics Formulas, Symbols and Circuits mini notebook. Below is a
link to a screenshot of my simulation schematic / transient output.
http://admin.mvhosted.com/pulse_generator.JPG
-- VG1 is just a unit step, going from 0V to 5V at 1ms
---
I've been going through some of the circuits in the notebook, trying
to figure out how they work, etc.. In doing so, after thinking I knew
how they worked, I was testing them out using both pspice, and tina
ti, to see if they were working as I thought, etc... A good portion of
the circuits in the notebook don't seem to work in simulation though,
or at least not for me. I was wondering if it's an error on my part,
or if the models in the simulators are just too ideal for some of
these circuits to produce the proper outputs in simulation?
So, back to the pulse generator. I was thinking about it for a few
hours and after the simulation didn't work as expected, I built the
circuit on a breadboard and tested it out with my tek 475 scope. I
unfortunately only have one probe, which is making it hard for me to
get a grasp on what's going on - having to move the scope probe from
point to point, etc...
---
My real question is how does everyone else look at this type of a
circuit? And, does anyone have any tips I could use to better figure
circuits like this out at first glance ( or even a few quick
calculations )?
When I first looked at the circuit it seemed like it might not work.
It seemed to me that the PNP transistor would always be on - at 1ms
( when VG1 goes to 5V and the voltage across C1 is 0V ) the base would
be biased to 5V-0.6V ~ 4.4V right? ( current would be flowing at this
point through the cap ). I was thinking this would be enough to turn
the PNP on, which would then turn the NPN on. It would seem like C1
would continue to charge up until there was some sort of a balance
between the current flowing into the collector of the NPN and the
current flowing through C1 - and maybe that is how this circuit works
( but I'm still not sure ).
With regard to the simulation - it looks like the left side of C1 is
pulled to 0V, the right side of C1 is pulled to 4.4V via D1, and then
a steady state condition is reached in the circuit where both the PNP
and NPN are always on. This does seem flawed to me, but I've been
thinking that if I was ever to try and design my own circuits ( even
something similar to this ), it would be extremely tedious to have to
do it on a breadboard each time - it would be nice to rough things out
in a simulation program first.
When I was testing the circuit on the breadboard, the voltage drop
accross C1 was oscillating accross 0V by a very slight amount. It
seemed like this was what was causing the PNP or NPN to turn on for
the short pulse duration. I'm still not sure how this is working
though ( I'm having a hard time visualizing it working ) - to me it
seems that the PNP would always be on due to the 1.5M resistor to
ground, and that the base of the PNP would seem to have a biasing
voltage of at least 5V-VD1-VR2~4.4V ( Veb ~ 0.6V, should be enough to
turn the eb diode in the PNP on ). With the PNP on, the NPN would be
on and it would seem like the output would always just be 5V-VD1~4.4V.
Obviously this is not the case as I've tested it on the breadboard and
it works as advertised in the engineer's notebook, which is why I'm
posting this question to you.
Any help, tips or insights would be most helpful,
Best Regards,
Morgan
I know this is probably a rather trivial question / circuit for most
people in this group, but since I'm having a hard time visualizing
exactly what is going on in the circuit I was hoping someone here
might not mind giving me some additional insight into what is going
on.
The circuit is the 2 transistor Pulse Generator from Forrest Mim's
Electronics Formulas, Symbols and Circuits mini notebook. Below is a
link to a screenshot of my simulation schematic / transient output.
http://admin.mvhosted.com/pulse_generator.JPG
-- VG1 is just a unit step, going from 0V to 5V at 1ms
---
I've been going through some of the circuits in the notebook, trying
to figure out how they work, etc.. In doing so, after thinking I knew
how they worked, I was testing them out using both pspice, and tina
ti, to see if they were working as I thought, etc... A good portion of
the circuits in the notebook don't seem to work in simulation though,
or at least not for me. I was wondering if it's an error on my part,
or if the models in the simulators are just too ideal for some of
these circuits to produce the proper outputs in simulation?
So, back to the pulse generator. I was thinking about it for a few
hours and after the simulation didn't work as expected, I built the
circuit on a breadboard and tested it out with my tek 475 scope. I
unfortunately only have one probe, which is making it hard for me to
get a grasp on what's going on - having to move the scope probe from
point to point, etc...
---
My real question is how does everyone else look at this type of a
circuit? And, does anyone have any tips I could use to better figure
circuits like this out at first glance ( or even a few quick
calculations )?
When I first looked at the circuit it seemed like it might not work.
It seemed to me that the PNP transistor would always be on - at 1ms
( when VG1 goes to 5V and the voltage across C1 is 0V ) the base would
be biased to 5V-0.6V ~ 4.4V right? ( current would be flowing at this
point through the cap ). I was thinking this would be enough to turn
the PNP on, which would then turn the NPN on. It would seem like C1
would continue to charge up until there was some sort of a balance
between the current flowing into the collector of the NPN and the
current flowing through C1 - and maybe that is how this circuit works
( but I'm still not sure ).
With regard to the simulation - it looks like the left side of C1 is
pulled to 0V, the right side of C1 is pulled to 4.4V via D1, and then
a steady state condition is reached in the circuit where both the PNP
and NPN are always on. This does seem flawed to me, but I've been
thinking that if I was ever to try and design my own circuits ( even
something similar to this ), it would be extremely tedious to have to
do it on a breadboard each time - it would be nice to rough things out
in a simulation program first.
When I was testing the circuit on the breadboard, the voltage drop
accross C1 was oscillating accross 0V by a very slight amount. It
seemed like this was what was causing the PNP or NPN to turn on for
the short pulse duration. I'm still not sure how this is working
though ( I'm having a hard time visualizing it working ) - to me it
seems that the PNP would always be on due to the 1.5M resistor to
ground, and that the base of the PNP would seem to have a biasing
voltage of at least 5V-VD1-VR2~4.4V ( Veb ~ 0.6V, should be enough to
turn the eb diode in the PNP on ). With the PNP on, the NPN would be
on and it would seem like the output would always just be 5V-VD1~4.4V.
Obviously this is not the case as I've tested it on the breadboard and
it works as advertised in the engineer's notebook, which is why I'm
posting this question to you.
Any help, tips or insights would be most helpful,
Best Regards,
Morgan
