Hi all,
I have an analog signal (0-5v) that is normally stable or slowly
changing. I want to design a simple circuit (analog and digital)
that triggers a line when a strong variation occurs in a period
of time.
For example, if in 10 minutes the signal change from 3V to 1V,
than a signal must be raised from 0 to 1 in order to wake-up a
microcontroller. After doing its work, micro untriggers the digital
signal and goes in sleep mode again.
It's important to trigger a digital line on a strong variation on
an analog signal. I can do that with micro and internal ADC, but I
want it in sleep mode.
---
If you connect your changing signal, VIN, to a resitive voltage
divider,:
VIN>---+
|
[R1]
|
+--->VOUT1
|
[R2]
|
GND>---+--->GND
Then the amplitude changes of VOUT1 will follow the amplitude changes
of VIN and will be in phase with them.
Now, if Vout1 is connected to an integrator,:
VIN>--+
|
[R1]
|
+-----+----->VOUT1
| |
| [R3]
| |
[R2] +----->VOUT2
| |
| [C1]
| |
GND>--+-----+----->GND
then as VIN changes amplitude, the amplitude of VOUT2 will also
change, but more slowly than VOUT1. That is, it will always _lag_
VOUT1. As a consequence of that, and with two exceptions, while VIN
is rising the voltage at VOUT1 will always be higher than the voltage
on VOUT2, and when VIN is falling, the voltage at VOUT1 will always be
lower than the voltage on VOUT2. The exceptions are If VIN was rising
and then starts to fall or if it was falling and then starts to rise,
when it will take a little while for VOUT2 to catch up. So, if VIN
was rising and then starts to fall there will be a short time between
when VOUT1 starts to fall and when it actually gets lower than VOUT2
and, conversely, if if VIN was falling and then starts to rise, there
will be a short time between when VOUT1 starts to rise and when it
actually gets higher than VOUT2, but for this application I don't
think that matters.
Now, assuming that VIN is stable and that you want to start a timing
interval by setting VOUT1 equal to VOUT2 we can do that by momentarily
shorting them together like this:
VIN>--+
|
[R1]
|
+-----+---+-->VOUT1
| | |
| [R3] O
| | |
| O-->|S1
[R2] |
| +------>VOUT2
| |
| [C1]
| |
GND>--+-----+------>GND
Now, (neglecting C1's leakage current) as soon as C1 charges to VOUT1,
the switch can be opened, no current will flow through R3 and, as long
as VIN doesn't move, VOUT1 will stay equal to VOUT2.
Let's hook this stuff up to a window comparator:
VIN>--+
| VCC
[R1] |
| [R6]
+------------------|-\ |
| | >--+----->DOWN
[R2] +--|+/
| S1 | U1A
+----O-->| |
| | | VCC
+--[R5]--O------+ |
| | [R7]
[R3] +--|-\ |
| | | >--+----->UP
+---------------|--|+/
| | U1B
[R4] [C1]
| |
GND>--+---------------+-------------->GND
We've added R2 and R3, equal value low resistance resistors for the
purpose of setting U1A- slightly more positive than U1A+ and U1B+
slightly more negative than U1B- when S1 is closed. This will make a
little window which will assure that the output of both comparators
will be low when S1 is closed or when when the voltage on C1 falls
within the window.
Now, (with S1 open) if we ramp up VIN to a more positive voltage, the
voltage on C1 won't be able to follow instantaneously, so the voltage
on U1A- and U1B+ will go more positive than the voltage on U1A+ and
U1A-. Since the voltage on U1A- was already more positive than the
voltage on U1A+ its output will stay low. However, if the time rate
of change of the ramp voltage is great enough, U1B+ will go more
positive than U1B-, forcing the output of U1B high for as long as the
ramp can stay far enough ahead of the changing voltage on C1. The
speed at which C1 charges and discharges is set by the voltage
difference between the ramp voltage and the voltage on C1, the
resistance of R5, the capacitance of C1, the currents associated with
the leakage current of C1 and the bias currents of the comparators so,
to a first approximation, it's RC.
Just like the output of U1A will be low and the output of U1B will
high while the ramp woltage is rising, the output of U1A will go high
and the output of U1B will go low when the ramp voltage is falling.
Then, since the output of both comparators is low when VIN is stable,
these three outputs can be used to control an up-down counter used as
a timer. That is, when both outputs are low inhibit the counter, when
U1B goes high force the counter to count up, and when U1A goes high
force the counter to count down.
Then, by using another comparator to set the zero-time point,
(momentarily closing S1 or its non-mechanical equivalent) another to
detect the voltage limit, and a magnitude comparator to detect the
counter timeout, you can do whatever you need to before you wake up
the micro. For instance, you could easily detect the condition you
described by detecting that the voltage had gone past its limit in the
time allocated since the voltage limiter comparator's output would
have gone true before the magnitude comparator's output did.
Although the implementation of hysteresis hasn't been addressed,
although you must surely consider it if your input voltage will be
varying slowly, and to do it properly you'll probably have to change
the sense of one comparator and decode the two outputs to reflect that
sense change.