The DLL clock buffers in the newer Xilinx FPGAs can be programmed for
negative propagation delay!
Sure. The clock carries no information so it can go FTL. ;-)
Now if I just build a long shift register,
and run the stock ticker data through...
....been done. There was an interesting insider attack on the horse
racing pari-mutual industry too. They only got caught because they
were a little too greedy and (un)lucky (several long-shots came in).