The joys of MIPS on PICs

[Randy Day]

I'm at the low end of the learning curve on
PIC32 assembler programming (I know, I know,
'masochist', etc., etc.

The following code compiles, but the branch
instruction doesn't work; it just goes to
the instruction after the branch.

mainloop:
lw $t0, 0
addu $t0, 2
b mainloop

I tried 'j mainloop', and got the same thing.
What am I not understanding here?

 

[Jon Kirwan]

I'm at the low end of the learning curve on
PIC32 assembler programming (I know, I know,
'masochist', etc., etc.

The following code compiles, but the branch
instruction doesn't work; it just goes to
the instruction after the branch.

mainloop:
lw $t0, 0
addu $t0, 2
b mainloop

I tried 'j mainloop', and got the same thing.
What am I not understanding here?

I haven't used the PIC32 and haven't even bothered looking up
the assembly language manual for it yet, but I seem to recall
that it is like MIPS RISC -- per your thread title. If so,
there may be a "branch delay slot" in the PIC32. Are you
aware of this possibility? (The branch delay slot is the
instruction following a branch, which is always executed as
well.) When you say "it just goes to the instruction after
the branch" it's not clear to me that you understand this
about MIPS designs (starting with the R2000, memory serving.)

Jon

 

[Randy Day]

[snip]

I haven't used the PIC32 and haven't even bothered looking up
the assembly language manual for it yet, but I seem to recall
that it is like MIPS RISC -- per your thread title. If so,
there may be a "branch delay slot" in the PIC32. Are you
aware of this possibility? (The branch delay slot is the
instruction following a branch, which is always executed as
well.) When you say "it just goes to the instruction after
the branch" it's not clear to me that you understand this
about MIPS designs (starting with the R2000, memory serving.)

You could be right about the branch delay slot.
I kept stepping through with the simulator, and
it would hop to the next instruction every time,
at which point I'd stop and say something, er,
unpleasant.

I'll try stepping a bit further next time.

Thanks!

 

[Jon Kirwan]

[snip]

I haven't used the PIC32 and haven't even bothered looking up
the assembly language manual for it yet, but I seem to recall
that it is like MIPS RISC -- per your thread title. If so,
there may be a "branch delay slot" in the PIC32. Are you
aware of this possibility? (The branch delay slot is the
instruction following a branch, which is always executed as
well.) When you say "it just goes to the instruction after
the branch" it's not clear to me that you understand this
about MIPS designs (starting with the R2000, memory serving.)

You could be right about the branch delay slot.
I kept stepping through with the simulator, and
it would hop to the next instruction every time,
at which point I'd stop and say something, er,
unpleasant.

I'll try stepping a bit further next time.

Thanks!

No problem. I loved working on the R2000 in the mid 1980's
and getting to meet Hennessey and getting a personal tour for
a day back when MIPS was a tiny start-up on the bottom floor
of a newish building near Weitek, back then. I'm just going
from memory here, not having ever used a PIC32. But I'm kind
of betting this is the issue at hand and I hope it works out
that this concept explains your observations satisfactorily.

Jon