phil said:
Is it possible to test if a FET transistor is o.k. with an ohmmeter,
i.e. with bipolar we simply check that the two diodes are o.k.
but with FET we do not have this npn structure, so what do we
do?
Using your finger on MOSFET devices can blow the gate due to static buildup.
Here are some simple tests:
N-MOSFET enhancement, get two 1k ohm resistors and a normally open push
button. Hook the gate and drain up to 10V through separate 1k ohm resistors,
and the source to ground. The source should be close to 0. Now, hook up the
push button between the gate and ground. When you push the button, the
source pin should shoot up to 10V. When you release it, it should go back
down to near 0. If you can measure the voltage accurately (call it V), when
the button isn't pushed, the Rds should be around 1000*V/(10-V).
10V
|
+---+----+
| |
.-. .-.
1k | | | | 1k
| | | |
'-' '-'
| | Vdrain
| +--------------o
| |
| ||-+D
| ||<- N-MOSFET (enhancement)
+----G||-+S
| |
| o |
|=|> |
| o |
| |
+--------+
|
===
GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta
www.tech-chat.de
P-MOSFET enhancement, same circuit, except exchange 10V and GND everywhere
in the description.
N-JFET, its a depletion device, which contains diodes. A diode tester will
give you a Vf if you hook the gate to the + and either source or drain to
the - terminal. However, depending on the JFET and tester, this might not be
good for the JFET.
Another way to test it is by running it. You can do this by hooking up the
source to the gate should let current flow. If you lower the gate voltage
below the source, it should turn off. So, hook up a 1k resistor between the
source and ground. Hook the drain to 10V, and the gate to the source. The
voltage at the source should be fairly close to 10V. Call this Vsource. If
you then hook up the gate to gnd, the voltage at the gate should drop to
near 0. Assuming you measure Vsource, then the Idss (which is the 0V
current) should be Vsource/1000.
10V
+
|
|
|
SPDT |
|--------o |-+D
| __--oG->| N-JFET
| |---o |-+S
| | | Vsource
| --------------+-------------o
| |
| .-.
| | | 1k
| | |
| '-'
| |
+---------+--------+
GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta
www.tech-chat.de
Again, reverse the GND and 10V to test a P-JFET.
Note that you can destroy a JFET by forward biasing the gate and channel, so
make sure you never make the gate of a N-JFET greater than 0.6V than either
source or drain.
Regards,
Bob Monsen