A
Andrew Holme
A colleauge of mine is building an automated test jig for measuring rise
times under different capacitive loads ranging from 5 to 70pF. Switching
small capacitances with relays is difficult/impossible and I proposed he use
electronic switching. Here are the schemes we've considered:
.-- 1V step from 100-ohm source impedance
| 10ns rise time (unloaded)
| -------o-----------------o----------------o----> To 'scope
| | | |
--' --- --- ---
C1 --- C2 --- C3 --- R3 10k
| | | ___
.-----o | o----|___|-> +10V
| | | |
L1 C| | PIN |/ |/
1uH C| V Diode .----| Q1 .----| Q2
C| - D1 | |> | |>
| | | | | |
.-. | .-. | .-. |
R1 | | === R2 | | === R3 | | ===
120 | | GND 1k | | GND 1k | | GND
'-' '-' '-'
| | |
| | |
3.3V Level CMOS Logic Control Lines
C1/C2/C3 in 15 - 50pF range
Q1/Q2 = 2SC4774 or BFS20W
Our first thought was to use PIN diode switching; but we see problems with
the above circuit in simulation when the diode is supposed to be off. Large
negative DC bias is required to stop the fast rise time of the signal
turning on the diode; and, unless an impractically large inductance is
specified, choke L1 passes a sizeable AC current, causing severe waveform
distortion.
The bipolar transistor circuit seems much better. There is no waveform
distortion except for the expected RC low-pass filtering effect of the
selected load capacitance. The output capacitances of the 2SC4774 and
BFS20W are both specified as about 1pF at Vcb = 10V; however, it seems to
work equally well in simulation with or without DC collector bias.
Any comments or advice?
TIA
times under different capacitive loads ranging from 5 to 70pF. Switching
small capacitances with relays is difficult/impossible and I proposed he use
electronic switching. Here are the schemes we've considered:
.-- 1V step from 100-ohm source impedance
| 10ns rise time (unloaded)
| -------o-----------------o----------------o----> To 'scope
| | | |
--' --- --- ---
C1 --- C2 --- C3 --- R3 10k
| | | ___
.-----o | o----|___|-> +10V
| | | |
L1 C| | PIN |/ |/
1uH C| V Diode .----| Q1 .----| Q2
C| - D1 | |> | |>
| | | | | |
.-. | .-. | .-. |
R1 | | === R2 | | === R3 | | ===
120 | | GND 1k | | GND 1k | | GND
'-' '-' '-'
| | |
| | |
3.3V Level CMOS Logic Control Lines
C1/C2/C3 in 15 - 50pF range
Q1/Q2 = 2SC4774 or BFS20W
Our first thought was to use PIN diode switching; but we see problems with
the above circuit in simulation when the diode is supposed to be off. Large
negative DC bias is required to stop the fast rise time of the signal
turning on the diode; and, unless an impractically large inductance is
specified, choke L1 passes a sizeable AC current, causing severe waveform
distortion.
The bipolar transistor circuit seems much better. There is no waveform
distortion except for the expected RC low-pass filtering effect of the
selected load capacitance. The output capacitances of the 2SC4774 and
BFS20W are both specified as about 1pF at Vcb = 10V; however, it seems to
work equally well in simulation with or without DC collector bias.
Any comments or advice?
TIA