Hi,
Does anybody worked with SirfAtlasV processor? I'm wondering what ECC algorythm is using in this chip to work with NAND flash? I know (from datasheet) that this processor is using (in case of 2048 page size) BCH ECC 21 bit per 1024 sector. First of all I found only one implementation of BCH alg. in Linux mtd driver, and tried different settings of this alg but failed. I have a NAND dump (so I have an original data and ECC from OOB).
If somebody have any information please help.
P.S. Maybe somebody know, is there any development board with this processor?
Does anybody worked with SirfAtlasV processor? I'm wondering what ECC algorythm is using in this chip to work with NAND flash? I know (from datasheet) that this processor is using (in case of 2048 page size) BCH ECC 21 bit per 1024 sector. First of all I found only one implementation of BCH alg. in Linux mtd driver, and tried different settings of this alg but failed. I have a NAND dump (so I have an original data and ECC from OOB).
If somebody have any information please help.
P.S. Maybe somebody know, is there any development board with this processor?
