Simple? logic function using 74HC logic

[Francois Grieu]

Hello,

I'm struggling to find a simple schematic to implement this two-inputs (A B),
one output (X) function, using 74HC building blocks.

In words:
- X is high whenever A and B are both high;
- if A is high when B goes low, X tracks B until A and B are both high;
- if A is low when B goes low, X remains high.

A-----------\__________________/--------\_______/---\___/--------------

B------\________/---\_____/-----------------\______________/-----------

X-------\________/---\_____/-------------------------------------------


The B to X delays must be low, in the order of 50 ns max @ 5V, for both
transitions. A / B setup times are in the order of 200 ns min.

Any idea ? So far anything I can think of has some ugly delay/monostable.

TIA,

Francois Grieu

 

[Jasen Betts]

Hello,

I'm struggling to find a simple schematic to implement this two-inputs (A B),
one output (X) function, using 74HC building blocks.

In words:
- X is high whenever A and B are both high;
- if A is high when B goes low, X tracks B until A and B are both high;
- if A is low when B goes low, X remains high.

A-----------\__________________/--------\_______/---\___/--------------

B------\________/---\_____/-----------------\______________/-----------

X-------\________/---\_____/-------------------------------------------


The B to X delays must be low, in the order of 50 ns max @ 5V, for both
transitions. A / B setup times are in the order of 200 ns min.

Any idea ? So far anything I can think of has some ugly delay/monostable.

for minimum propogation delay you need to do it like this.

A -----::::::::::::::::: or gate
::state machine::------. __
B -+---::::::::::::::::: `--| \
| ) 1 >--------
| .--|__/
`--------------------------'

it looks like the state machine is an S-R flip-flop

with (A & B) feeding RESET and (B & !A) feeding SET



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[Francois Grieu]

for minimum propogation delay you need to do it like this.

A -----::::::::::::::::: or gate
::state machine::------. __
B -+---::::::::::::::::: `--| \
| ) 1 >--------
| .--|__/
`--------------------------'
Agreed.

it looks like the state machine is an S-R flip-flop

Seems reasonable...

with (A & B) feeding RESET and (B & !A) feeding SET

Unless I err, the second pulse is missing from X.

A----------------\__________________/-------\_______/---\___/---------

B-----------\________/---\_____/----------------\______________/------

R=A&B-------\_______________________/-------\__________________/------

S=B&!A_______________/---\_____/----\_______/---\_____________________

SR___________________/--------------\_______/------------------\______

X'=B|SR------\________/-----------------------------------------------

X------------\________/---\_____/-------------------------------------

The SET condition seems overly inclusive. But I have trouble pinpointing
an appropriate condition. I think it can't be a purely combinatorial
function of A and B.


Francois Grieu

 

[Francois Grieu]

John Fields wrote :

Unless I'm missing something, and you're talking something other than
combinatorial logic,

I'm indeed talking something other than pure combinatorial logic.
The state of the output X depends on previous history of the inputs,
not only on the present state of the inputs.

My previous "words" statement was imprecise, and one case not
illustrated in the diagram; things should have been:
- X is high and the system reset whenever A and B are both high;
- if A is high when B goes low, then X shall track B until system reset;
- otherwise, X shall remain high.

A--------\__________________/----\_______/---\___/-------\___________/----

B----\________/----\___/-------------\_______________/-------\___/--------

X-----\________/----\___/-------------------------------------------------


In precisely equivalent words, X is to be high if and only if
- B is high
OR
- there has been no high to low transition of B with A high since
the last time the condition (A and B) held.

The B to X delays must be low, in the order of 50 ns max @ 5V, for both
transitions. There is only a single change of either A or B in any
200 ns time period.

Francois Grieu

 

[Uwe Hercksen]

Any idea ? So far anything I can think of has some ugly delay/monostable.

Hello,

a simple solution using only gates and no delay or monostables is
impossible.
But may be there is a solution using gates and edge triggerd flipflops.
If you use a falling edge triggerd flipflop and connect A to the clock
input and B to the data input, the Q output remains high if A goes low
before B. But you get a problem with the second fallig edge of A while B
is low.

Bye

 

[Francois Grieu]

Tim Wescott a écrit :

What happens when A goes low?

That alone never changes the output.

My previous "words" statement was a bit imprecise, and one case not
illustrated in the diagram; things should have been:
- X is high and the system reset whenever A and B are both high;
- if A is high when B goes low, then X shall track B until system reset;
- otherwise, X shall remain high.

A--------\__________________/----\_______/---\___/-------\___________/----

B----\________/----\___/-------------\_______________/-------\___/--------

X-----\________/----\___/-------------------------------------------------

It needs internal states, and it either needs to be clocked damn fast or
(as someone mentioned) it needs those internal states to feed gates that
control X from B.
Yes.

How many internal states do you need?

Just one bit S: has there been a high-to-low transition on B with A set
since the last time the condition A&B held. Then X = B | !S.

Can you clock this thing from an asynchronous clock

No, because the single clock at hand is not fast enough, and besides B
has no defined phase relationship with that clock.

or does it have to be clocked by the edges of A and B?

That's what I'm looking after.


Francois Grieu

 

[Helmut Sennewald]

Hello,

I'm struggling to find a simple schematic to implement this two-inputs (A
B),
one output (X) function, using 74HC building blocks.

In words:
- X is high whenever A and B are both high;
- if A is high when B goes low, X tracks B until A and B are both high;
- if A is low when B goes low, X remains high.

A-----------\__________________/--------\_______/---\___/--------------

B------\________/---\_____/-----------------\______________/-----------

X-------\________/---\_____/-------------------------------------------


The B to X delays must be low, in the order of 50 ns max @ 5V, for both
transitions. A / B setup times are in the order of 200 ns min.

Any idea ? So far anything I can think of has some ugly delay/monostable.

TIA,

Francois Grieu

Hello Francois,

You should use an FF to build a small state machine.

A solution with a theoretical positive edge clock input D-FF with positiv
reset:

CLK = B\
D = A OR Q
CLR = Q AND A AND B

X = (Q AND B) OR Q\


WIth a real FF 74HC74 with positive edge clock-input and low reset:

CLK = B\ -> Inverter 74HC14
D = A OR Q --> 1/4 74HC32
CLR\ = (Q AND A AND B)\ --> 1/3 74HC10

X = (Q AND B) OR Q\ --> (1/3 74HC10 +Inverter) + 1/4 74HC32

You should use a 74HC14 for the inverters to get fast edges,
especially if your A and B inputs have rise times slower than 100ns.

Best regards,
Helmut


PS: You would save the OR-Gate at the D-input if you use a JK-FF.

 

[Jasen Betts]

Seems reasonable...


Unless I err, the second pulse is missing from X.

A----------------\__________________/-------\_______/---\___/---------

B-----------\________/---\_____/----------------\______________/------

R=A&B-------\_______________________/-------\__________________/------

S=B&!A_______________/---\_____/----\_______/---\_____________________

SR___________________/--------------\_______/------------------\______

X'=B|SR------\________/-----------------------------------------------

X------------\________/---\_____/-------------------------------------

The SET condition seems overly inclusive. But I have trouble pinpointing
an appropriate condition. I think it can't be a purely combinatorial
function of A and B.

You're right. I was thinking on this further, more state is needed so
that the flipflop is only set when A goes from high to low while B is high.

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