seeking explanation on basic led flashing circuit

[stuzero]

hello,

im new to electronics and i would like to understand a simple circuit im building as shown below:
it's led flashing circuit using 2 transistor Q1 npn and Q2 pnp. my question is why the transistors would ever go off at all. i think the circuit may seem very basic to every electronic people as it could be found anywhere. still i think the circuit could be stable at both transistors ON and no flashing?

if i try using ideal transistor for Q1 on circuit wizard simulation, it won't flash. (Q1 could still ON with base current about 1 uA from the 5M base resistor without capacitor feeding current, right?) flashing occurs only if i use realistic Q1 model such as 2N3904. so there is some realistic behavior that i miss? anyone pls help explain or pls point me a reference that i should study to understand why this works.

thank you for helping with this very basic question.
stuzero

 

[Bluejets]

Old blokes like me find something small like that to be a bit hard to read.....

 

[stuzero]

thanks for point that out.
is this better?

 

[Bluejets]

Not into Circuit Wizard sorry...

 

[KrisBlueNZ]

It's a two-transistor relaxation oscillator. It's described in various places on the web. I ran a search: https://www.google.com/search?q=two transistor relaxation oscillator -unijunction -multivibrator -ujt&tbm=isch and found the following relevant pages:

http://www.covingtoninnovations.com/michael/blog/0502/#050203
http://www.paia.com/bckit1/theory.asp (includes a brief explanation)
http://embeddeddreams.com/site/2008/10/06/fun-and-easy-to-build-buzzer-circuit/

 

[stuzero]

It's a two-transistor relaxation oscillator. It's described in various places on the web. I ran a search: https://www.google.com/search?q=two transistor relaxation oscillator -unijunction -multivibrator -ujt&tbm=isch and found the following relevant pages:

http://www.covingtoninnovations.com/michael/blog/0502/#050203
http://www.paia.com/bckit1/theory.asp (includes a brief explanation)
http://embeddeddreams.com/site/2008/10/06/fun-and-easy-to-build-buzzer-circuit/
http://embeddeddreams.com/site/2008/10/06/fun-and-easy-to-build-buzzer-circuit/

i appreciate your help kris

 

[Bluejets]

So , what is the difference between "ideal" and "realistic" ....just curious..

 

[stuzero]

after browsing thru above places. i still dont quite get the concept:
re: http://www.paia.com/bckit1/theory.asp
"once our 2N4401 transistor is turned on, we use it to turn on a second transistor, providing more amplification and the correct voltage swing to help shut off the capacitor's base voltage for the 2N4401 transistor. When the second transistor turns on, that transistor tries to connect the battery cell V+ to the speaker wire. When that happens, the voltage on the speaker wire is pulled up. This also jerks up the capacitor's other leg which is connected to the speaker wire.
As soon as that leg of the capacitor is jerked up, this causes the voltage on the base-connected side to quickly drop. This kills the current into the base of the 2N4401, so it shuts off."

maybe i dont understand the language of this explanation: if "jerking up the capacitor other leg" means raising voltage, how could that results in the base voltage to quickly drop?
what i thought is the capacitor discharges and kills the base current after both Q1 and Q2 are already OFF, so making Q1 firmly OFF further before re-charging phase?
most of the explanations i found so far do not clarify how the transistor Q1 was cut OFF in the first place (and causing capacitor to discharge not vice versa?)
and why ideal transistors would not trigger such oscillation.

i would also appreciate if anyone can show the original analysis in the following piece i found in krisblue's suggestion:

 

[stuzero]

So , what is the difference between "ideal" and "realistic" ....just curious..

im curious on that too, got to check circuit wizard references.
probably ideal ones would exhibit zero cutoff ib, zero sat voltage, horizontal curve and "something" else.
the realistic ones are selected from list of commercial models.

 

[KrisBlueNZ]

OK, I'll try to explain the two-transistor relaxation oscillator. I ran an LTSpice simulation with the following schematic:


The simulation generated the following waveform at Q1B:



As you can see, I had to set the initial conditions so Q1B was at 0V, otherwise LTSpice starts the simulation with the circuit in a stable state and it won't start oscillating! Also, this is the simplest version of the two-transistor relaxation oscillator, and RL must be fairly low and RT fairly high, so Q2 eventually falls out of saturation, otherwise again, it won't oscillate.

So the circuit starts with both transistors OFF, with Q1B = 0V and CT discharged. Current from QT charges CT and Q1B rises until Q1 begins to conduct and bias Q2 ON as well. When Q2 starts to conduct and the Q2C voltage starts to rise, the increasing voltage is coupled through CT and reinforces the increasing voltage at Q1B, driving both transistors into saturation.

According to the simulation, which uses an ideal battery with zero ESR, the Q1 collector / Q2 base current peaks at about 100 mA here. This is one weakness of this simple version of the circuit, and there are at least four places where a resistor can be inserted to reduce this heavy current.

Here's a zoomed version of the positive spike and trail-off at Q1B during the time that Q2 is conducting:



As you can see, Q1B peaks very briefly at almost the full 3V! This peak corresponds to a current of over 100 mA into Q1's base. This is another disadvantage of this circuit!

During this time, CT is being charged the opposite way - the Q2C voltage is higher than Q1B. CT's charge current (coming from Q2, and going into Q1's base) drops as CT charges. The Q1B voltage rapidly drops, then levels off at about 800 mV then drops and starts to tail off. When it has fallen to about 630 mV, Q1 comes out of saturation; Q2 also comes out of saturation, and the Q2C voltage starts to drop.

A similar positive feedback action occurs here; as Q2C falls, the drop is coupled through CT onto Q1B, turning Q1 OFF even more, and the circuit rapidly flips to the opposite state, with both transistors OFF. At this time though, CT is charged to nearly 2V (the Q2C end positive with respect to the Q1B end), so this pushes Q1B negative. This is why this circuit shouldn't be used with a power supply voltage of more than about 6V - the negative base-emitter voltage on Q1 will cause conduction of the base-emitter junction zener diode and this will damage Q1.

QT again begins to charge through RT, and the Q1B voltage rises through 0V and up towards Q1's base-emitter conduction voltage again, and the cycle repeats indefinitely.

 

[stuzero]

thanks a lot for your details.
but im still not clear regarding this instant:
"When it has fallen to about 630 mV, Q1 comes out of saturation; Q2 also comes out of saturation, and the Q2C voltage starts to drop."

what mechanism drives Q1B and Q2C to drop further? can they just stop short steadily at the original 630 mV level (as CT fully charged)? i mean can Q1B just reduce to point 2 and stop there just like point 1 at the start of conduction? everything would be in equilibrium with all the Q2 current draining to RL.

is there some kind of inertial component that causes overshrinking during this voltage drop?

wishing you help clarify further.
(also, the spike of Q1B voltage coincides with the start of LED flash right? just to confirm.)

i think i get the concept of astable multivibrator since that one has no steady state. but this 2Q relaxation oscillator has a possible steady state. am i right?

 

[KrisBlueNZ]

In that simple version of the oscillator, both transistors are so heavily saturated at the start of the condition time that the duration of the conduction period is actually mostly determined by the charge storage time in both transistors, as you can see from this graph:



The green trace shows Q1B using the scale markings on the left. When conduction starts, it spikes at around +3V, but it rapidly trails off. The cyan trace shows Q1's base current, using the scale on the right, and as you can see, it falls to zero very quickly as well. The red trace, using the scale on the right, shows the Q1 collector current (and Q2 base current; they're the same). You can see that it doesn't start to fall until some time after Q1's base current has dropped to around zero.

This is caused by charge storage in Q1, and a similar effect can be seen due to charge storage in Q2 because the Q1B voltage (which is coupled to Q2C) doesn't start to fall immediately either. (Don't ask me to explain charge storage; I don't understand semiconductor physics.)


It's easier to understand the circuit when saturation in the transistors is reduced. To do this, I added a 10 kΩ resistor, RD, in series with CT, to limit the Q1 base current and Q1 saturation, and a 300Ω resistor, R1, to limit Q2's saturation. I had to increase RT to 1 MΩ and reduce CT to 330 pF to make the circuit oscillate at roughly the same frequency as before.


Here's the Q1B waveform:



... and here's a close-up of the active period, showing the Q1B voltage, Q1 base current, and Q1 collector current:



The red trace, Q1's collector current, starts to take off as Q1 begins to conduct (due to rising base voltage as CT charges through RT). This immediately causes conduction in Q2, and Q2C rises, coupling the increase back to Q1B and causing the bump in the cyan trace.

But now, Q1's base current (cyan trace) is limited by RD, and it peaks at only about 250 µA. This still saturates Q1 and its collector current (red trace) rises rapidly to about 6.5 mA.

As Q1's base current tapers off, Q1 falls out of saturation and its collector current (red trace) drops. A short time after it reaches zero, Q2 begins to turn OFF too, as evidenced by the rapid drop in the Q1B voltage (caused by the rapid fall in Q2C, coupled through CT).

With CT now charged with the Q1B side negative relative to the Q2C side, and Q2C pulled down to 0V by RL, Q1B is now negative and CT must charge in the other direction, through RT, before another conduction event will occur.

(also, the spike of Q1B voltage coincides with the start of LED flash right? just to confirm.)

Right.

i think i get the concept of astable multivibrator since that one has no steady state. but this 2Q relaxation oscillator has a possible steady state. am i right?

Yes, but it won't reach the steady state during normal operation. It will enter the stable state if CT is removed. That second circuit, with CT removed, stabilises at the following point:

Q1B voltage = 646 mV
Q1C and Q2B current = 714 µA
Q2C current = 112.9 mA
Q2C voltage = 1.13V

 

[stuzero]

thanks again for your great explanation.
if you may, is my following slow-thinking comprehension correct?

1. i think the transistor storage time is probably the key element for oscillation:
at the first part of active time, even with the end of Q1B spike, Q2 in particular still remains conducted and saturated and thus feeding CT to its maximum voltage.
after the "storage time", Q2 in particular comes out of saturation. although Q1 and Q2 still not yet OFF, Q2C current drops quickly as well as the voltage across RL.
but, CT voltage still is at its maximum; therefore, CT will discharge back thru RL.
this short burst of CT discharging brings Q1B down, turns Q1 (then Q2) OFF completely, and triggers even further drastic drop in Q1B.

2. the storage time in data sheet is only around 100 ns. but from your chart, the time delay is about 10 order of magnitude larger, probably from other elements such as lead wire?

3. simulation using "ideal" transistors does not show oscillation, probably because without storage time delay?

 

[KrisBlueNZ]

1. i think the transistor storage time is probably the key element for oscillation:
at the first part of active time, even with the end of Q1B spike, Q2 in particular still remains conducted and saturated and thus feeding CT to its maximum voltage.

I assume you're talking about the simple design in post #10?

Yes, after the initial sharp spike on Q1B, both transistors remain saturated. Q1 remains saturated because of its charge storage time, and Q2 remains saturated because Q1 is saturated.

after the "storage time", Q2 in particular comes out of saturation. although Q1 and Q2 still not yet OFF,

No, I don't think so. Have a look at the first graph in post #12. That graph applies to the simple design. After the initial 3V spike on Q1B, the first significant thing that happens is Q1's collector current (which is also Q2's base current) falling away rapidly. This happens when Q1's charge storage time expires and Q1 starts to turn OFF. Until this happens, Q2 has heavy base bias and will remain saturated.

The next thing that happens is Q2's charge storage time expiring; when that happens, the Q2C voltage falls towards 0V, and CT couples the falling voltage back to Q1B, producing the fall on the green trace, from about 0.6V to about -2.1V.

So Q1 turns OFF before Q2 even begins to turn OFF. The charge storage times add together.

Q2C current drops quickly as well as the voltage across RL. but, CT voltage still is at its maximum; therefore, CT will discharge back thru RL.

No, I don't see what you're saying. Q2C drops to 0V and CT has about 2.1V across it, so it pulls Q1B negative, to about -2.1V. Q1's base-emitter junction is reverse-biased and will not conduct (unless the supply voltage is high enough to cause zener breakdown in that junction), so the only current path is through RT, which causes the gradual rising voltage at Q1B that eventually reaches Q1's base-emitter voltage and starts the next cycle. But there is no rapid charge or discharge of CT at that part of the cycle.

this short burst of CT discharging brings Q1B down, turns Q1 (then Q2) OFF completely, and triggers even further drastic drop in Q1B.

No, I don't think so. At the point in the cycle where Q2 is turning OFF, and Q2C is falling towards 0V, CT simply couples the falling voltage from Q2C to Q1B. This does reinforce the change that caused Q1 to turn OFF, but Q1 is already fully OFF, and Q2's base current has fallen to zero, so there is no positive feedback at this part of the cycle. Q2 turns OFF in its own time (helped by the low value of RL), then the Q1B voltage starts to ramp up again from -2.1V towards +0.6V.

2. the storage time in data sheet is only around 100 ns. but from your chart, the time delay is about 10 order of magnitude larger, probably from other elements such as lead wire?

No, stray capacitance will not be significant. The Fairchild 2N3904 data sheet gives a charge storage time of 200 ns when the collector current is 10 mA and the base current is 1 mA. In this circuit, both of those currents are much higher, especially the base current, and especially for Q2. I think that would be the reason.

3. simulation using "ideal" transistors does not show oscillation, probably because without storage time delay?

Does your simulator have an equivalent of the .ic (initial conditions) directive? If so, try setting the inital condition for Q1B to 0V. Otherwise the simulator may try to find the steady-state equilibrium point for the circuit and once it gets stuck there, it won't start oscillating by itself.

Edit: Also, try the version with the extra resistors, if you haven't already.

 

[Colin Mitchell]

There are a couple of points that have not been emphasised.
The first point is the fact that the second transistor must be in a high-current situation so that it requires a high base current at some point in the cycle.
The second feature to visualise is the fact that the capacitor is doing all the work of turning the first transistor ON and OFF. The high value resistor on the base of the first transistor is only there to start the cycle and slowly discharge (charge) the capacitor.
The cycle starts by the resistor on the base of the first transistor charging the capacitor and producing a voltage of 550mV on the base.
This starts to turn ON the first transistor and this transistor starts to turn on the second transistor.
The voltage on the collector of the second transistor starts to rise and the energy on (in) the capacitor is passed to the base of the first transistor to turn it ON more.
Both transistors now start to turn ON more and the voltage on the collector of the second transistor rises and all the charge in the capacitor flows into the base of the first transistor. The two transistors keep turning ON and now the right lead of the capacitor is higher than the voltage on the base of the first transistor so that the capacitor immediately changes from delivering energy into the base of the first transistor to a condition where it is receiving energy from the base-emitter junction of the first transistor and the transistor turns ON even more. Even though the capacitor is changing from a state of discharging to a state of charging, the flow of electrons through the base-emitter of the first transistor does not change direction or reduce. The flow constantly increases.
This continues until the second transistor cannot turn ON any more and the voltage on the right lead of the capacitor does not rise any more.
At this point both transistors are fully turned ON. But mainly it is the second transistor that decides this condition and the voltage on the two leads of the capacitor does not change.
But the capacitor charges a little more and in doing so, the current into the capacitor decreases.
This means the current-flow in the base-emitter junction of the first transistor reduces and it turns off a small amount.
The collector-emitter current reduces and this reduces the base-emitter current of the second transistor.
The causes the emitter-collector current of the second transistor to reduce and because the collector load of the second transistor is very SMALL the reduced current causes a CONSIDERABLE drop in voltage across the collector-load.
This makes the right-hand lead of the capacitor drop a small amount and the left lead drops by the same amount.
A drop of 50mV or so on the base of the first transistor has an enormous effect on turning it off and that’s why both transistors turn off very quickly at this part of the cycle.
The capacitor can be charged to a voltage of anything up to 2 volts and it mainly depends on the voltage on the collector load of the second transistor.
The two transistors have now turned off fully and the right lead of the capacitor falls by as much as 2v.
This makes the left lead fall by 2v and the base of the first transistor sees a voltage of about -2v.
What happens next is the high value resistor on the base of the first transistor gradually charges the capacitor in the reverse direction (you can call it discharging the capacitor) and the voltage rises from -2v to +550mV to start the cycle again.

 

[KrisBlueNZ]

Hey Colin! That's a pretty good description! I just have a few comments.

The voltage on the collector of the second transistor starts to rise and the energy on (in) the capacitor is passed to the base of the first transistor to turn it ON more.

It's not really a matter of "energy in" CT being "passed to" Q1B. The important characteristic about a capacitor is that the voltage across it can only change when current flows through it, or vice versa, kind of like a battery. So it tends to keep a constant voltage across itself. When Q2's collector voltage starts to rise, that rise is coupled to Q1's base by CT, and as we know, produces a positive feedback path that reinforces the conduction of both transistors.

Because this forward-biases Q1's base-emitter junction, a pretty high current flows through Q2, through CT, and into Q1 base. This current causes the voltage across CT to change rapidly, so that while the Q2C side remains close to VCC (2.8~2.9V in the simulation), the Q1B side falls quickly (from +3V to below +1V within ~55 ns, in my simulation) and quickly levels off at around 0.8V.



This graph shows Q1's base voltage (green trace) and base current (blue trace) from the onset of conduction in the transistors. Q1's base current (blue) peaks around 107 mA but has dropped below 10 mA within just 50 ns. During that time, the voltage across CT has changed from about 0.5V (Q1B side positive) to about 1.8V (Q2C side positive).

The two transistors keep turning ON and now the right lead of the capacitor is higher than the voltage on the base of the first transistor so that the capacitor immediately changes from delivering energy into the base of the first transistor to a condition where it is receiving energy from the base-emitter junction of the first transistor and the transistor turns ON even more.

Again that's a false distinction; the energy flows into Q1 base because the Q2C voltage is rising and CT "tries" to keep a constant voltage across itself.

Even though the capacitor is changing from a state of discharging to a state of charging, the flow of electrons through the base-emitter of the first transistor does not change direction or reduce. The flow constantly increases

If you think of it my way, there's no need to explain why the direction of current flow is always from Q2 into Q1's base - that's obvious.

But the capacitor charges a little more and in doing so, the current into the capacitor decreases. This means the current-flow in the base-emitter junction of the first transistor reduces and it turns off a small amount.

Actually the Q1 base current has already dropped below 10% of its peak within 50 ns of the start of saturation. It is charge storage in both transistors that keeps them both saturated for another 6 µs or so. It's an important distinction because charge storage plays a role, though I don't think it's a necessary part of the circuit's operation.

The collector-emitter current reduces and this reduces the base-emitter current of the second transistor. The causes the emitter-collector current of the second transistor to reduce and because the collector load of the second transistor is very SMALL the reduced current causes a CONSIDERABLE drop in voltage across the collector-load. This makes the right-hand lead of the capacitor drop a small amount and the left lead drops by the same amount.

A drop of 50mV or so on the base of the first transistor has an enormous effect on turning it off and that’s why both transistors turn off very quickly at this part of the cycle.

I think you're right about that, if I understand what you're saying.

So you're talking about the point in the graph above where the green trace (Q1B voltage) is starting to fall, and causes a rapid drop on the red trace (Q1's collector current)?

So as Q2 starts to come out of saturation and Q2C voltage starts to fall, this fall is coupled through CT into Q1's base and forces Q1 to start to come out of saturation. This causes its collector current to fall and this causes a positive feedback situation during the last part of the conduction time.

That makes sense to me. So the last part of the conduction pulse, where Q2 remains pretty heavily saturated as its base current is falling off, is not due to charge storage in Q2 at all. Thanks for clearing that up!

The two transistors have now turned off fully and the right lead of the capacitor falls by as much as 2v. This makes the left lead fall by 2v and the base of the first transistor sees a voltage of about -2v. What happens next is the high value resistor on the base of the first transistor gradually charges the capacitor in the reverse direction (you can call it discharging the capacitor) and the voltage rises from -2v to +550mV to start the cycle again.

Right.

 

[Colin Mitchell]

"It's not really a matter of "energy in" CT being "passed to" Q1B."

That's one of the most important points.
The capacitor is already charged to 650mV and this energy is removed from the capacitor during the time when the two transistors start to turn ON.

"This current causes the voltage across CT to change rapidly,
That is completely wrong.
The voltage across the load increases and this causes the right lead of the capacitor to rise. The left lead cannot rise any more as it is fixed by the base-emitter voltage of the first transistor.
The increasing voltage across the capacitor causes an increased current to flow in the capacitor - NOT THE CURRENT CAUSES THE VOLTAGE ACROSS THE CAPACITOR TO INCREASE.

"Again that's a false distinction; the energy flows into Q1 base because the Q2C voltage is rising and CT "tries" to keep a constant voltage across itself."

Where do you get that fairy-tail from ????

The energy DOES NOT flow into the base of Q1 during the part of the cycle we are currently explaining. .

"Actually the Q1 base current has already dropped below 10% of its peak within 50 ns of the start of saturation."

Don't bring nS into this when we are talking about mS and seconds.

"If you think of it my way, there's no need to explain why the direction of current flow is always from Q2 into Q1's base - that's obvious."

It's NOT obvious because the capacitor is changing from charging to discharging and it is not obvious that the current-flow in the base-emitter junction of the first transistor remains in the same direction. That's why I emphasised it. It's because the base is effectively "stuck" at a voltage or potential of 0.65v that the capacitor has to first-of-all discharge into the base and as the capacitor discharges, it maintains the 0.65v.
Now, when the capacitor rises to 0.65v, it does not deliver any energy to the first transistor, so the high-value base resistor "gets it over the hump" by adding a microscopic amount of energy and now the right lead of the capacitor is above 0.65v and it wants to get charged via the base-emitter junction of the first transistor.
This is the most crucial and important part of the discussion as no-one has ever explained how the two transistors get turned ON, in fine detail. No-one has ever said the base-resistor assists and this is the CRUX of the whole cycle. Otherwise the circuit would stop at the point where the right lead is 0.65v.

 

[KrisBlueNZ]

Oh dear :-( Bring back the Colin who seemed to understand the circuit. I was beginning to like him.

 

[davenn]

Oh dear :-( Bring back the Colin who seemed to understand the circuit. I was beginning to like him.

haha .... was just a brief flash ... blink and you missed it