J
John Hudak
Hi Folks:
I've been away from this area for a while and am looking for opinions &
facts regarding current CAD tools for digital ckt design and analysis.
In the past (1990s) I've used ORCAD, Protel, and Eagle 3.x for circuit
capture, board layout and routing. I also used some tools for logic
design and analysis at the gate level (e.g. ABLE for PALs and Verilog).
So my question is this: Are there any tools that combine techniques
for capturing state and timing information and do the associated
analysis? (EEWorkbench?). For example...I am designing a CPU and
associated memory hierarchy (cache, main, etc). At the functional pin
level for instruction fetch, I want to simulate a memory write sequence
(how the CPU pins would be cycled), simulate the memory address decoding
logic (however implemented), and memory cycles. So, what I want to be
able to do is specify the cpu pin signals for a mem-rd cycle, mem-write,
read-modify-write, etc. simulate the decode logic all the way to the
memory interface for the purpose of verifying the memory access (decode)
is correct over the entire memory space (both physical and virtual
address). I also want to be able to analyze it from a timing
perspective (to include as little or much detail about the paths as I
want to (i.e. setup/hold times, prop delay, etc.).
The last time I attempted this (1997?) I had to use several tools to do
different aspects. So I am wondering if any tool vendor has integrated
this into their systems? Also, any comments on the current packages
(ORCAD, Protel, and Eagle) are welcome.
Thanks
John
I've been away from this area for a while and am looking for opinions &
facts regarding current CAD tools for digital ckt design and analysis.
In the past (1990s) I've used ORCAD, Protel, and Eagle 3.x for circuit
capture, board layout and routing. I also used some tools for logic
design and analysis at the gate level (e.g. ABLE for PALs and Verilog).
So my question is this: Are there any tools that combine techniques
for capturing state and timing information and do the associated
analysis? (EEWorkbench?). For example...I am designing a CPU and
associated memory hierarchy (cache, main, etc). At the functional pin
level for instruction fetch, I want to simulate a memory write sequence
(how the CPU pins would be cycled), simulate the memory address decoding
logic (however implemented), and memory cycles. So, what I want to be
able to do is specify the cpu pin signals for a mem-rd cycle, mem-write,
read-modify-write, etc. simulate the decode logic all the way to the
memory interface for the purpose of verifying the memory access (decode)
is correct over the entire memory space (both physical and virtual
address). I also want to be able to analyze it from a timing
perspective (to include as little or much detail about the paths as I
want to (i.e. setup/hold times, prop delay, etc.).
The last time I attempted this (1997?) I had to use several tools to do
different aspects. So I am wondering if any tool vendor has integrated
this into their systems? Also, any comments on the current packages
(ORCAD, Protel, and Eagle) are welcome.
Thanks
John
