There is afaik no defined upper limit on the number of devices connected to an SPI bus.
The max. bus capacitance depends on the driver strength of the components used and the clock frequency.
The higher the clock frequency, the less time is available for charging or discharging the bus capacitance, therefore a smaller capacitance is allowed.
The higher the driver strength, the faster the bus capacitance is charged or discharged, therefore a higher bus cpacitance is allowed.
As far as I know these limits are not defined per standard. You'll have to look up the parameters in the datasheets of the components used.