Regarding driving of SCL and SDA pins of I2C

[[email protected]]

Hi all,

This is a basic qustion regarding SDA and SCL pins.
Since both these pins are bidirectional these should pins need to be
tristated , so that the slave can acknowledge on SDA.

But i have seen in some docs that a '1' need to be converted to a 'Z'
while driving on SDA and SCL, what is the reason behind this????

Thanks in advance,
Praveen

 

[Antti Lukats]

Hi all,

This is a basic qustion regarding SDA and SCL pins.
Since both these pins are bidirectional these should pins need to be
tristated , so that the slave can acknowledge on SDA.

But i have seen in some docs that a '1' need to be converted to a 'Z'
while driving on SDA and SCL, what is the reason behind this????

Thanks in advance,
Praveen

well in order to drive '1' (EXERNAL RESISTIVE PULLUP) you need to Z the wire
eg tristate it.
0 is driven as 0
1 is driven (or relased) as Z, ext pullup will pull the wire high

Antti

 

[Fred]

Hi all,

This is a basic qustion regarding SDA and SCL pins.
Since both these pins are bidirectional these should pins need to be
tristated , so that the slave can acknowledge on SDA.

But i have seen in some docs that a '1' need to be converted to a 'Z'
while driving on SDA and SCL, what is the reason behind this????

Thanks in advance,
Praveen

They're not tri-stated as such, merely a pull down or open collector output,
with an external resistive pull-up. If using a micro or FPGA then set the
output to a "0" and use the tri-state enable to turn the pin on or off.

 

[Mark Jones]

Hi all,

This is a basic qustion regarding SDA and SCL pins.
Since both these pins are bidirectional these should pins need to be
tristated , so that the slave can acknowledge on SDA.

No, both pins are not bidirectional. Only the master device drives the SCK
line, and all slaves must leave their SCK's as input.

But i have seen in some docs that a '1' need to be converted to a 'Z'
while driving on SDA and SCL, what is the reason behind this????

Thanks in advance,
Praveen

As others have said, usually SCK and SDA have a 1-10k pullup resistor to Vdd.
This makes the signal a 1 while no device is pulling a pin low. So set the
output pin to a zero, and toggle it as being an input versus an output, to
generate your digital signal.

Since SCK is never "tristated", you can just drive it as 0/1 output using the
master device and omit the pullup resistor. Of course, the master device must be
able to source and sink a few mA. The PIC line of microcontrollers have no
problem doing this; the Atmels probably work the same.

Furthermore, if the Atmels have a pin which is "open collector output only",
then that would work for SDA without needing to tristate it. Just set it as an
output and "0" will pull SDA low, and "1" will release it (alowing the pullup
resistor to make SDA "1".)

For power-hungry applications, you can increase the pullup resistors at the
expense of speed and noise rejection. 100k works well for shielded,
battery-powered applications.

Cheers,
MCJ

 

[Kryten]

No, both pins are not bidirectional. Only the master device drives the SCK
line, and all slaves must leave their SCK's as input.

Yes, they are.

Slaves can pull down SCL to 'wait state' traffic to match their own speed.

That's why it has to be open-collector.

Since SCK is never "tristated", you can just drive it as 0/1 output using
the
master device and omit the pullup resistor.

No, this is seriously against the spec!

You should never drive it active high.

Otherwise slaves may be damaged when they try to wait-state the bus master.


I've heard this bad advice before - people say they get away with it, but
they cannot say it obeys the I2C spec.

 

[James Beck]

No, both pins are not bidirectional. Only the master device drives the SCK
line, and all slaves must leave their SCK's as input.

Not true, a slave device can extend a cycle through clock stretching and
the only way to do that is for the slave device to be able to hold the
clock line low.

http://www.i2c-bus.org/clockstretching/

 

[Mark Jones]

Not true, a slave device can extend a cycle through clock stretching and
the only way to do that is for the slave device to be able to hold the
clock line low.

http://www.i2c-bus.org/clockstretching/

Explain that to a Noob.

Please.

 

[[email protected]]

No, both pins are not bidirectional. Only the master device drives the SCK
line, and all slaves must leave their SCK's as input.

I do not agree with u mark

If a slave can't
receive or transmit another complete byte of data until it
has performed some other function, for example servicing
an internal interrupt, it can hold the clock line SCL LOW to
force the master into a wait state.

 

[[email protected]]

well in order to drive '1' (EXERNAL RESISTIVE PULLUP) you need to Z the wire
eg tristate it.
0 is driven as 0
1 is driven (or relased) as Z, ext pullup will pull the wire high

In order to drive a '1' , i will not tristate it to 'Z' i will drive a
'1' only.
Any issues(Hardware malfunction) if i drive a'1' instead of 'Z'

 

[Keith]

You can read a summary here:

http://www.i2c-bus.org/Termination.277.0.html

But I recommend visiting the Philips site and downloading the
specification:

http://www.semiconductors.philips.com/markets/mms/protocols/i2c/

You can probably safely ignore the multimaster and high-speed modes,
but you should be aware of their existance. I personally don't know of
anybody using high-speed mode, but it does make the I/O requirements
more interesting.

-Keith

 

[Keith]

You can find everything that you want to know at the Philips site:

http://www.semiconductors.philips.com/markets/mms/protocols/i2c/

I recommend that you download and read the specification first. You can
probably safely ignore anything related to multimaster or high-speed
mode, but be aware that these exist. They also have discussion forums
where you can ask questions.

-Keith

 

[Bob Monsen]

Explain that to a Noob.

Please.

A slave device can use the clock as a primitive flow control mechanism.

If the slave takes some amount of time to process a byte, it can prevent
the master from starting the next byte by simply holding the clock low.
The master cannot clock the data until the clock is released by the slave.

I2C clocks are not really clocks, they are 'data valid' signals. They
don't have to go at any a particular rate, and aren't constrained by
anything except setup and hold times for the devices.

Regards,
Bob Monsen

 

[Bob Monsen]

Hi all,

This is a basic qustion regarding SDA and SCL pins.
Since both these pins are bidirectional these should pins need to be
tristated , so that the slave can acknowledge on SDA.

But i have seen in some docs that a '1' need to be converted to a 'Z'
while driving on SDA and SCL, what is the reason behind this????

Thanks in advance,
Praveen

You need a primer in I2C.

If you are the only master, and drive the SDA wire to 1, nothing bad will
happen unless, the slave thinks it's supposed to ack at the wrong time, at
which time you'll get a short between the master and slave. The standard
specifies resistors you can add to keep the devices from getting damaged
in this case.

However, you CANNOT drive SCL to 1, because a slave is allowed to hold you
off by driving it low. You have to notice this, so driving it high is not
going to work unless you make the clock slow enough so that the slave will
never hold you off.

In most I2C applications, the bus and clock should only go high when
nobody is pulling it low.

There are 'fast' modes of I2C which may not obey this restriction.
However, a device starts off in the pullup mode, and then switches over, I
believe.

 

[Antti Lukats]

In order to drive a '1' , i will not tristate it to 'Z' i will drive a
'1' only.
Any issues(Hardware malfunction) if i drive a'1' instead of 'Z'

YES, the other poster. The master should drive 0 and Z at least on the SDA
pin
and only in the case that there is no multimastering and no clock stretching
it is ok to drive 0 and 1 on the SCL

antti

 

[James Beck]

Explain that to a Noob.

Please.

Click on the link please.
That's why I included it, or do you mean you don't understand what the
link is explaining?