Re: Root Cause of FDC6303N FET drain and gate short circuit?

[Winfield Hill]

Myauk wrote...

In a typical PCBA design which consists of relay driver circuit, we
found the FET drain and gate short circuit problem causing damage to
MCU DIOs due to excessive sink current in production on 5 or 6 failed
out of 100 PCBA units.

2. Or is there any possible fault condition which can cause a good
working FET to have gate and drain shorted?

Drain-to-gate shorts is a typical failure mode for power mosfets.

Amusingly, the mosfet is still probably operating properly, that
is it's operating the same as any other mosfet with its drain and
gate externally connected together. But I digress.

You want to know why the part failed. SFAIK, any of the various
overstress conditions can cause this type of failure. E.g.,
overheating, in any of the ways Rds(on), switching losses,
avalanche heating, or overvoltage. Including gate overvoltage,
which can happen if a high current is switched too fast, causing
high dI/dt, and a substantial source-wiring inductance, causing
high V = L dI/dt, which can be a short damaging gate-voltage spike.

Lot's of handwaving there, but the standard remedies apply, a diode
across the coil, a gate resistor to slow down switching speed, etc.

 

[tm]

Myauk wrote...

..But I think it is not really a design issue. We have already added
..freewheeling diode verifying the back emf is already eliminated by
..checking the waveforms. And 10k Gate resistor is there. So there is no
..way possibly to damage the FET.
..
..Does anyone have similar experience?
..
..Thanks and Best Regards

If you have a 10k gate resistor, how is it killing the DIO?

 

[tm]

.But I think it is not really a design issue. We have already added
.freewheeling diode verifying the back emf is already eliminated by
.checking the waveforms. And 10k Gate resistor is there. So there is no
.way possibly to damage the FET.
.
.Does anyone have similar experience?
.
.Thanks and Best Regards

If you have a 10k gate resistor, how is it killing the DIO?

..Current from 5 V supply through relay is approximately 60mA sinking
..into the LOW Dio pin rated at 15mA. (4 times the rated value).

Then there is something you are not telling us. From your two comments, you
say the
MCU DIO pin connects to the fet through a 10k resistor. If the fet shorts to
5 volts
(g to d), then the max current can be 0.5 mA. I=E/R= 5/10000=0.0005

Maybe you need to draw us a picture.


T

 

[SoothSayer]

Myauk wrote...


Drain-to-gate shorts is a typical failure mode for power mosfets.

Amusingly, the mosfet is still probably operating properly, that
is it's operating the same as any other mosfet with its drain and
gate externally connected together. But I digress.

You want to know why the part failed. SFAIK, any of the various
overstress conditions can cause this type of failure. E.g.,
overheating, in any of the ways Rds(on), switching losses,
avalanche heating, or overvoltage. Including gate overvoltage,
which can happen if a high current is switched too fast, causing
high dI/dt, and a substantial source-wiring inductance, causing
high V = L dI/dt, which can be a short damaging gate-voltage spike.

Lot's of handwaving there, but the standard remedies apply, a diode
across the coil, a gate resistor to slow down switching speed, etc.

I always noticed on year, when doing a huge amplifier design, which
contained a row of huge IGBTs and FETs on a 20 inch long sink, that we
had some odd failures early on in the design that had no reason for
being...

Early failure modes were tied to coplanarity issues on the sink. It
seems our assembler did not understand the concept of coplanarity until I
showed him the proper assembly sequence. Without it, it was as if any
part that did get attached right was not attached at all.

Anyway, we experienced plenty of what appeared to be "immediate"
failures due to the lack of a part being sinked properly. It was really
a matter of a few seconds. and went away once assembly efficacy was
achieved.

It seems that those thermal spikes were fast enough to take the part to
critical failure temperatures. Good heat sinking is REQUIRED, and that
right where it belongs... on the back of that tab!

 

[SoothSayer]

Thanks Win,

But I think it is not really a design issue. We have already added
freewheeling diode verifying the back emf is already eliminated by
checking the waveforms. And 10k Gate resistor is there. So there is no
way possibly to damage the FET.

Does anyone have similar experience?

Thanks and Best Regards

Do you have a thermal imager?

If not, you could rent one. Examine the device as you utilize it.
Watch the failure mode as it occurs and examine the waveforms during that
period to determine if it is circuit design related of heat management
related.

Make sure that your heat sink attachment has a high integrity thermal
pathway. Do not simply use a dry, "air" attachment. Make sure that it is
well sinked.

Once you rule out that, then get back to probing the circuit.

Have you ever used 'transzorbs', or put ferrite beads on the gate lead
during assembly? As close to the part as possible.

 

[tm]

.Current from 5 V supply through relay is approximately 60mA sinking
.into the LOW Dio pin rated at 15mA. (4 times the rated value).

Then there is something you are not telling us. From your two comments,
you
say the
MCU DIO pin connects to the fet through a 10k resistor. If the fet shorts
to
5 volts
(g to d), then the max current can be 0.5 mA. I=E/R= 5/10000=0.0005

Maybe you need to draw us a picture.

T

..10k resistor is the parallel pull down resistor between gate and
..source of FET.
..
..There is no resistance, the DIO directly drives the FET Gate.
..
..Regards

I would at least put a small resistance, say 100 ohms or so, in series
with the gate to PIO pin. I'm not sure why you need the pull down as the
MCU should drive it ok. Unless the MCU three states the pin prior to
completing the reset. What bypassing are you using in the circuit? MCU?
Fet?


Regards,
T

 

[Hammy]

I would at least put a small resistance, say 100 ohms or so, in series
with the gate to PIO pin. I'm not sure why you need the pull down as the
MCU should drive it ok. Unless the MCU three states the pin prior to
completing the reset. What bypassing are you using in the circuit? MCU?
Fet?


Regards,
T

I use a pull down when driving FET's directly off a PIC as well. Most
uC's on start-up default to input so a pull down ensures the FET stays
off. I usually use 220k Bleeder gate to source or higher though.

Its a pretty low threshold FET are you sure your Vgs is going low
enough to completely turn it off especially with a 10k pull down?

I don't know what uC your using but the worst case LOW on an I/O for a
PIC can be as high as 0.6V At as little as 1.2mA. I've never seen it
that high but it is the worst case.

You would figure a rupture of the gate oxide from over voltage would
cause it to fail open. I've never had a FET fail that way usually when
I blow one its pretty spectacular and obvious. ;-)

You really want to keep the loop for the gate source signal small as
well as the drain source loop to reduce trace inductance. You should
be using a gate resistor 4.7 to 22 ohm or a fusible resistor may be
better in this case;-)

Oh and just because your not seeing ringing doesnt mean it isnt, you
may just need a higher BW scope to see it. The gate oxide of such a
low threshold fet wouldnt be to tolerant to overvoltage transients.