Question about folded cascode

[[email protected]]

I wanted to design folded cascode opamp in picture...
http://img246.imageshack.us/img246/5915/gjhhgkil4.jpg
I have used allen's book: with his method i obtain a great gain, but a
very bad offset. To reduce offset usually i reduce W of cascode load
(L is fixed in my project), but Voutmin is also reduced...how can i
obtain the same gain with little offset?
I've found that if W7 is greater than W6, offset is greatly reduced,
but i'm not really sure that is a correct way to resolve this problem:
this method is correct or not? Why?
Thanks for the help

 

[Winfield Hill]

I wanted to design folded cascode opamp in picture
http://img246.imageshack.us/img246/5915/gjhhgkil4.jpg
I have used allen's book: with his method i obtain a great gain, but
a very bad offset. To reduce offset usually i reduce W of cascode
load (L is fixed in my project), but Voutmin is also reduced...how
can i obtain the same gain with little offset?
I've found that if W7 is greater than W6, offset is greatly reduced,
but i'm not really sure that is a correct way to resolve this problem:
this method is correct or not? Why?

What did you do with M15, compared to M6 and M7, to be sure
that M3 and M4 have enough voltage to operate? M15, M6 and
M7 are all running at 1mA, and if these are identical transistors,
there won't be anything left for M3 and M4.

 

[[email protected]]

I wanted to design folded cascode opamp in picture...http://img246.imageshack.us/img246/5915/gjhhgkil4.jpg
I have used allen's book: with his method i obtain a great gain, but a
very bad offset. To reduce offset usually i reduce W of cascode load
(L is fixed in my project), but Voutmin is also reduced...how can i
obtain the same gain with little offset?
I've found that if W7 is greater than W6, offset is greatly reduced,
but i'm not really sure that is a correct way to resolve this problem:
this method is correct or not? Why?
Thanks for the help

Are you talking about offset in terms of monte-carlo analysis, or do
you have offset using the same model for each flavor of transistor?
That is, in real life, mismatch in M6/M7 causes input referred offset.
Higher transconductance in the long tail pair reduces this effect.

If you running this in spice and getting offset without introducing
variance in components, your circuit is probably not biased correctly.
You need to insure that under all conditions, VDS exceeds VDSAT.

I never used a folded cascode in real life, but the thing simulates
like a champ.

 

[[email protected]]

This is my circuit: i have used ideal voltage sources instead current
mirrors to reduce problems...
http://img186.imageshack.us/img186/6782/foldedat7.jpg
My circuit satisfy all requirements except the great offset voltage
(this is represented in picture). In this picture
http://img72.imageshack.us/img72/9734/satuationlt0.jpg
i have rapresented Vsd-Vsg+|Vp| of Q5 and Q7: so when this value is
greater than zero, transistor is in saturation region.
Vbias2 is obtained from condition on Voutmax: when Vout=Voutmax(=1.7V)
Q5 and Q7 are in saturation region and have the same Vsd (it is equal
to intersection point in second picture). Q5 is in saturation region
for a greater range then Q7, so i don't think that is the problem (i
am new in this field, so i'm not totally sure).
If Is5 increases, gain became smaller
If Vbias2 decreases, offset change slowly but Voutmax is greatly
reduced
If W of cascode load is reduced, offset is reduced but Voutmin also
As i have said, the only way to obtain good results is W7 greater than
W6, but i'm not totally sure on this solution...can you help me?
Thanks for the help

 

[[email protected]]

Is what you are calling "offset" the output of -1.262V ??

Yes, it's very big but i'm not able to eliminate it...any suggestion?

That's what it should be ;-)

I don't understand

 

[[email protected]]

Examine your circuit from the point of view of SYMMETRY.

By symmetry the output MUST BE -1.262V when the inputs are at equal
potentials, is that not so?

I'm confused...
if In+=In-, q4-6-8-10 have the same bias (current and voltage) values
of q5-7-9-11....
If I4,I1,Vbias1 and Vbias2 are fixed (by other requirements) =>I6=I4-
I1, Vsd4 and Vsd6 are known,so Vout is what it shoud be:it is what you
mean?

Keep in mind that you are dealing with perfectly matched devices.  In
the real world there should be enough gain to overcome that... high-Z
load.

Vout=-1.262V can be called offset or not?I've studied offset as output
voltage when In+=In-=0...is this right?
An offset like this, can be accepted or not? (i'm really new in this
field)

Otherwise think cascoding so that there is a ground reference on the
left side of the cascode structure.

Thanks for the suggestion...i'll try to implement it

 

[[email protected]]

This is my circuit: i have used ideal voltage sources instead current
mirrors to reduce problems...http://img186.imageshack.us/img186/6782/foldedat7.jpg
My circuit satisfy all requirements except the great offset voltage
(this is represented in picture). In this picturehttp://img72.imageshack.us/img72/9734/satuationlt0.jpg
i have rapresented Vsd-Vsg+|Vp| of Q5 and Q7: so when this value is
greater than zero, transistor is in saturation region.
Vbias2 is obtained from condition on Voutmax: when Vout=Voutmax(=1.7V)
Q5 and Q7 are in saturation region and have the same Vsd (it is equal
to intersection point in second picture). Q5 is in saturation region
for a greater range then Q7, so i don't think that is the problem (i
am new in this field, so i'm not totally sure).
If Is5 increases, gain became smaller
If Vbias2 decreases, offset change slowly but Voutmax is greatly
reduced
If W of cascode load is reduced, offset is reduced but Voutmin also
As i have said, the only way to obtain good results is W7 greater than
W6, but i'm not totally sure on this solution...can you help me?
Thanks for the help

Connect the positive input to ground and the negative input to the
output of the op amp. The output voltage will be the offset.

You are making this much more complicated than it really is.