PWM Demodulation (actual SED content)

[Tim Williams]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate
PWM, so I haven't bothered to look for things that have done my work
already).

One method that came to mind is to charge a capacitor while the input is
high, and discharge it while the output is low. Before discharging, the
voltage is forwarded to a sample & hold for output. Since I*dt = C*dV, this
works.

But, what if frequency is changing? The above is only pulse length, not
PWM, demodulation.

One option would be to demodulate the frequency as well, as an absolute
value, and multiply the PLM output . I thought of dividing the input by
two, to get a 50% duty cycle wave, then PLM demod it to obtain a value
corresponding to duration (1/f). The value then controls the charging
current for the integrator. Response, then, will be accurate every other
cycle.

But geez that's complicated.

Does this difficulty have anything to do with the spectrum of a PWM signal?
For sure, the key information -- DC bias -- is well below the carrier and
harmonics, but purely the percent information is contained cycle-to-cycle,
so long as the frequency isn't also changing very rapidly. The usual way of
course is an LPF, but I want to think of ways avoiding that cumbersome time
constant.

Tim

 

[Tim Wescott]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate
PWM, so I haven't bothered to look for things that have done my work
already).

One method that came to mind is to charge a capacitor while the input is
high, and discharge it while the output is low. Before discharging, the
voltage is forwarded to a sample & hold for output. Since I*dt = C*dV, this
works.

But, what if frequency is changing? The above is only pulse length, not
PWM, demodulation.

One option would be to demodulate the frequency as well, as an absolute
value, and multiply the PLM output . I thought of dividing the input by
two, to get a 50% duty cycle wave, then PLM demod it to obtain a value
corresponding to duration (1/f). The value then controls the charging
current for the integrator. Response, then, will be accurate every other
cycle.

But geez that's complicated.

Does this difficulty have anything to do with the spectrum of a PWM signal?
For sure, the key information -- DC bias -- is well below the carrier and
harmonics, but purely the percent information is contained cycle-to-cycle,
so long as the frequency isn't also changing very rapidly. The usual way of
course is an LPF, but I want to think of ways avoiding that cumbersome time
constant.

Tim

Are you trying to do anything real, or is this an intellectual exercise?

Assuming you know the frequency before hand your cap charge/discharge
thingy, or any comb filter, would work. If you really wanted something
that would be wholly arbitrary you could charge one cap on the + part
and another on the -, then use (a - b) / (a + b). This has all sorts of
practical difficulties, but those would go away after about three beers.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google? See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

 

[John Larkin]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate
PWM, so I haven't bothered to look for things that have done my work
already).

One method that came to mind is to charge a capacitor while the input is
high, and discharge it while the output is low. Before discharging, the
voltage is forwarded to a sample & hold for output. Since I*dt = C*dV, this
works.

But, what if frequency is changing? The above is only pulse length, not
PWM, demodulation.

One option would be to demodulate the frequency as well, as an absolute
value, and multiply the PLM output . I thought of dividing the input by
two, to get a 50% duty cycle wave, then PLM demod it to obtain a value
corresponding to duration (1/f). The value then controls the charging
current for the integrator. Response, then, will be accurate every other
cycle.

But geez that's complicated.

Does this difficulty have anything to do with the spectrum of a PWM signal?
For sure, the key information -- DC bias -- is well below the carrier and
harmonics, but purely the percent information is contained cycle-to-cycle,
so long as the frequency isn't also changing very rapidly. The usual way of
course is an LPF, but I want to think of ways avoiding that cumbersome time
constant.

Tim

Just lowpass filter it, with an optimum filter. You can't do any
better if you want a continuous-time output.

John

 

[Rich Grise]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate ....
so long as the frequency isn't also changing very rapidly. The usual
way of course is an LPF, but I want to think of ways avoiding that
cumbersome time constant.

Oh. My first answer was going to be "an integrator". You'd have ripple,
which would be a trade-off between frequency and response time.

But you don't like time constants. OK. Find the fastest micro you can
with two separate timer capture inputs, and count microseconds. Scale the
two answers (time high & time low), maybe divide to get duty cycle, and
output the answer through a DAC.

Good Luck!
Rich

 

[Tim Williams]

Oh...did I mention, PICs can FOAD? ;-)

Tim

 

[colin]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate
PWM, so I haven't bothered to look for things that have done my work
already).

One method that came to mind is to charge a capacitor while the input is
high, and discharge it while the output is low. Before discharging, the
voltage is forwarded to a sample & hold for output. Since I*dt = C*dV, this
works.

But, what if frequency is changing? The above is only pulse length, not
PWM, demodulation.

One option would be to demodulate the frequency as well, as an absolute
value, and multiply the PLM output . I thought of dividing the input by
two, to get a 50% duty cycle wave, then PLM demod it to obtain a value
corresponding to duration (1/f). The value then controls the charging
current for the integrator. Response, then, will be accurate every other
cycle.

But geez that's complicated.

Does this difficulty have anything to do with the spectrum of a PWM signal?
For sure, the key information -- DC bias -- is well below the carrier and
harmonics, but purely the percent information is contained cycle-to-cycle,
so long as the frequency isn't also changing very rapidly. The usual way of
course is an LPF, but I want to think of ways avoiding that cumbersome time
constant.

Measure the length of the on period with your ramp - sample and hold idea,
Then do the same for the off period BUT use a current inversly proportional
to the voltage generated from the on pulse.
You shld then have a voltage wich is a function of on/off time but hopefully
independant of the period.


Colin =^.^=

 

[Fred Bartoli]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate
PWM, so I haven't bothered to look for things that have done my work
already).

One method that came to mind is to charge a capacitor while the input is
high, and discharge it while the output is low. Before discharging, the
voltage is forwarded to a sample & hold for output. Since I*dt = C*dV, this
works.

But, what if frequency is changing? The above is only pulse length, not
PWM, demodulation.

One option would be to demodulate the frequency as well, as an absolute
value, and multiply the PLM output . I thought of dividing the input by
two, to get a 50% duty cycle wave, then PLM demod it to obtain a value
corresponding to duration (1/f). The value then controls the charging
current for the integrator. Response, then, will be accurate every other
cycle.

But geez that's complicated.

Does this difficulty have anything to do with the spectrum of a PWM signal?
For sure, the key information -- DC bias -- is well below the carrier and
harmonics, but purely the percent information is contained cycle-to-cycle,
so long as the frequency isn't also changing very rapidly. The usual way of
course is an LPF, but I want to think of ways avoiding that cumbersome time
constant.

Tim

It would help to understand that a PWM signal is nothing else but a sampled
signal (with sample height encoded as the pulse width instead of pulse
height).
Hence, all the limitations which applies to sampled signal applies to PWM
signals. IE, your signal BW is at most half your PWM frequency.

A reasonably steep LPF slightly bellow 1/2 the PWM frequency will recover
*all* the information embedded in your signal.

Your PWM frequency is changing? Make your LPF cutoff below half the lowest
PWM frequency.

 

[Rich Grise]

On Fri, 25 Aug 2006 16:05:40 -0500, Tim Williams wrote:

On Fri, 25 Aug 2006 16:05:40 -0500, Tim Williams top-posted

Oh...did I mention, PICs can FOAD? ;-)

Tim

I said, "micro", as in "microprocessor(microcomputer)." I didn't say
anything about a "PIC". ;-)

Cheers!
Rich


excised content restored:

 

[Tim Williams]

"Fred Bartoli"

Your PWM frequency is changing? Make your LPF cutoff below half the lowest
PWM frequency.

Yeah, but the dynamic range of my application could go from 5 to 50kHz, and
things can happen faster than 2.5kHz cutoff when operating at 50kHz.

What kind of phase shift or delay would such a filter produce, anyway?

Tim

 

[Mochuelo]

It would help to understand that a PWM signal is nothing else but a sampled
signal (with sample height encoded as the pulse width instead of pulse
height).
Hence, all the limitations which applies to sampled signal applies to PWM
signals. IE, your signal BW is at most half your PWM frequency.

A reasonably steep LPF slightly bellow 1/2 the PWM frequency will recover
*all* the information embedded in your signal.

Plus some distortion. If the sampling is uniform, you'll get harmonic
and combinational distortion. With natural sampling, you will only
have combinational distortion.

 

[joseph2k]

I was thinking of ways to demodulate PWM (note: Google doesn't demodulate
PWM, so I haven't bothered to look for things that have done my work
already).

One method that came to mind is to charge a capacitor while the input is
high, and discharge it while the output is low. Before discharging, the
voltage is forwarded to a sample & hold for output. Since I*dt = C*dV,
this works.

But, what if frequency is changing? The above is only pulse length, not
PWM, demodulation.

As it literally measures pulse width (length) it truly is PWM demodulation.
Frequency changes are a separate issue.

One option would be to demodulate the frequency as well, as an absolute
value, and multiply the PLM output . I thought of dividing the input by
two, to get a 50% duty cycle wave, then PLM demod it to obtain a value
corresponding to duration (1/f). The value then controls the charging
current for the integrator. Response, then, will be accurate every other
cycle.

But geez that's complicated.

Frequency to voltage converters are simple, it had been reduced to a single
IC by the early 1970's. Using the output of the F-V converter to modulate
the integrator current in the PWM demodulator is trivial.

Does this difficulty have anything to do with the spectrum of a PWM
signal? For sure, the key information -- DC bias -- is well below the
carrier and harmonics, but purely the percent information is contained
cycle-to-cycle,
so long as the frequency isn't also changing very rapidly. The usual way
of course is an LPF, but I want to think of ways avoiding that cumbersome
time constant.

At this point you may want to use transconductance amplifiers (using the F-V
signal) to modulate the corner frequency of the LPF.

 

[Don Foreman]

"Fred Bartoli"


Yeah, but the dynamic range of my application could go from 5 to 50kHz, and
things can happen faster than 2.5kHz cutoff when operating at 50kHz.

So use a tracking filter -- but then the max rate at which frequency
can change becomes a relevant parameter.

You could recover frequency by producing pulses on rising edges, make
this a squarewave with a /2 (flipflop), control a clock oscillator
with that, a divide-by-100 and a PLL, and use a switched-capacitor
filter as National LMF100. The divide-by-100 is because the center or
corner freq of the filter is 1/50 of the clock frequency. With
this scheme your filter would self- tune to be optimal for the
frequency at the moment. The max expected frequency slewrate will
determine the required PLL bandwidth.

A tracking filter or cycle-by-cycle PWM demodulator could also be
realized with a single DSP chip of course, but then you'd need the
skill, software and equipment to write and debug DSP software and
"burn" a DSP chip.

What kind of phase shift or delay would such a filter produce, anyway?

Depends on the filter type -- Butterworth, Bessel, etc etc. Also
depends on the order of the filter -- so acceptable ripple in the
output is another relevant parameter.