Puzzling circuit in EDN design ideas (NE555 voltage to frequencyconverter)

[ShamShoon]

Can somebody help me understand the circuit in http://www.edn.com/article/CA6531584.html
an NE555 based voltage to frequency converter. I tried simulating the
circuit in LTSpice but couldn't get the NE555 to work.

The article says that first the capacitor will be charging with an
applied negative input voltage. So far so good. When the output
reaches a certain voltage the discharge transistor Q1 will turn on and
reduce the output voltage.

This is what I don't get. If the voltage is decreasing on the cap
after Q1 is turned on, we have now 3 currents at the negative input
junction of the OpAmp.

1) Q1 current going upside down
2) Input voltage current going from right to left through the
resistors P1,R1 (0 to a negative voltage)
3) Cap discharge current going from left to right (The only way I can
think of if the output voltage is decreasing).

So now we have at one junction, 3 positive currents going away from
the junction, which by KCL is impossible.

So what am I missing ??

Thank you.

 

[John Popelish]

Can somebody help me understand the circuit in http://www.edn.com/article/CA6531584.html
an NE555 based voltage to frequency converter. I tried simulating the
circuit in LTSpice but couldn't get the NE555 to work.

I don't think it works, either.

The article says that first the capacitor will be charging with an
applied negative input voltage. So far so good. When the output
reaches a certain voltage the discharge transistor Q1 will turn on and
reduce the output voltage.

This is what I don't get. If the voltage is decreasing on the cap
after Q1 is turned on, we have now 3 currents at the negative input
junction of the OpAmp.

The voltage on pin 2 of the opamp is a virtual ground, very
nearly zero volts. The discharge transistor can draw no
current from that node.

1) Q1 current going upside down
2) Input voltage current going from right to left through the
resistors P1,R1 (0 to a negative voltage)
3) Cap discharge current going from left to right (The only way I can
think of if the output voltage is decreasing).

So now we have at one junction, 3 positive currents going away from
the junction, which by KCL is impossible.

So what am I missing ??

An editor?

This line is completely wrong:
"As the voltage on C1 reaches two-thirds of VCC, the 555’s
internal discharge transistor opens, and the voltage on C1
returns to one-third the voltage of VCC, the lower
comparator threshold." Q1 turns on after the threshold
voltage exceeds 2/3rds of the supply voltage, not turns off.

But it doesn't matter, since there is no source of positive
current into the opamp inverting input, top run the miller
capacitor negatively. You would need a positive current
source switched on and off by Q1 (on when Q1 pulled low) to
make this work. I think they lost a PNP transistor in
translation.

 

[M. Hamed]

I don't think it works, either.

[snip]

Thanks John. Now I got some of my sanity back. I think the editors
should have done some verification before including it.

 

[John Larkin]

Can somebody help me understand the circuit in http://www.edn.com/article/CA6531584.html
an NE555 based voltage to frequency converter. I tried simulating the
circuit in LTSpice but couldn't get the NE555 to work.

The article says that first the capacitor will be charging with an
applied negative input voltage. So far so good. When the output
reaches a certain voltage the discharge transistor Q1 will turn on and
reduce the output voltage.

This is what I don't get. If the voltage is decreasing on the cap
after Q1 is turned on, we have now 3 currents at the negative input
junction of the OpAmp.

1) Q1 current going upside down
2) Input voltage current going from right to left through the
resistors P1,R1 (0 to a negative voltage)
3) Cap discharge current going from left to right (The only way I can
think of if the output voltage is decreasing).

So now we have at one junction, 3 positive currents going away from
the junction, which by KCL is impossible.

So what am I missing ??

Thank you.

Most of the EDN submitted circuits are crap. They're just filler, to
keep the "editorial" content up enough so they can ship ads at the
cheap "magazine" postal rate. They're all journalism types; what would
they know about electronics?

John

 

[Bob Monsen]

Can somebody help me understand the circuit in
http://www.edn.com/article/CA6531584.html
an NE555 based voltage to frequency converter. I tried simulating the
circuit in LTSpice but couldn't get the NE555 to work.

The article says that first the capacitor will be charging with an
applied negative input voltage. So far so good. When the output
reaches a certain voltage the discharge transistor Q1 will turn on and
reduce the output voltage.

This is what I don't get. If the voltage is decreasing on the cap
after Q1 is turned on, we have now 3 currents at the negative input
junction of the OpAmp.

1) Q1 current going upside down
2) Input voltage current going from right to left through the
resistors P1,R1 (0 to a negative voltage)
3) Cap discharge current going from left to right (The only way I can
think of if the output voltage is decreasing).

So now we have at one junction, 3 positive currents going away from
the junction, which by KCL is impossible.

So what am I missing ??

Thank you.

There seems to be an error in the schematic posted. Pin 7 should probably be
connected to the trigger/threshold node, not to the input of the opamp. I'm
guessing that they want to discharge the integrator cap when it gets to 2/3
of Vcc.

Regards,
Bob Monsen

 

[BobW]

I don't think it works, either.

[snip]

Thanks John. Now I got some of my sanity back. I think the editors
should have done some verification before including it.

The editors did their job. I didn't spot a single misspelled word.

Bob