Purpose of cap on collector

[acko1989]

Hi,

I made circuit from this schematic in attachment that turns on and of appliances using IR receiver TSOP1738 and CD4017. When there is a IR signal from TV remote (or other source), TSOP1738 will output 0 V, so PNP transistor will be on, so the signal will go to the CD4017 and output 1 (pin 2) will be enabled (turn on). This CD4017 turns on next output based on rising edge on clock pin (pin 14). Because output 2 (pin 4) is connected to reset (pin 15), when we press TV button second time, there will be HIGH signal to output 2 and therefore to reset, so CD4017 will start from beginning once again. I know that capacitor C1 (100uF) is to prevent multiple pulses from TV remote going to CD4017 (because TV remote output several pulses) that will turn on and off appliance multiple times. But, what is the purpose of capacitor C2 (0.1uF)?




[Mod note: put image inline for easier view]

 

[bertus]

Hello,

I do not see an attachment.
You can upload an imge using the "Upload a File" button.

Bertus

 

[davenn]

Hello,

I do not see an attachment.
You can upload an imge using the "Upload a File" button.

Bertus

it's there

 

[Nanren888]

Sorry not your question, but interesting circuit.
I only found a datasheet from Vishay which is brief.The equivalent circuit shows an NPN, grounded emitter, almost open collector (80K to rail). IN your circuit this drives directly a PNP base with emitter on the top rail. The data sheet says 5mA output, 250mV output low. Maybe that means current limited, rather than maximum current?
Also the data sheet suggests some power supply smoothing with 100 Ohm in the supply line and a 4.7uF capacitor smoothing. Your circuit has the resistance in the line, but no smoothing.
All in all, an interesting circuit.
Might look for others to see if they do similar.
A quick looks shows multiple circuits that put a resistor between the tsop1738 output and the PNP base, as might be expected.
The TSOP seems to be aimed to accurately represent the IR pulses at the output, so as you suggest prevention of multiple triggering is relevant. Have not looked at the time constants for C1 and C2. Are they doing the same thing, effectively pulse shaping from mutliple input pulses?

 

[Nanren888]

 

[Harald Kapp]

This circuit is imho not well designed:

1. As @Nanren888 noted there is no current limiting resistor between the output of th eir receiver and the base of the pnp transistor. While the output of the ir receiver may be limited in max. current, it is not a good design to rely on such an undocumented feature (which will probably vary between manufacturers of a seemingly identical component).
2. C1 and C2 both are, I think, meant to filter the pulsed ir signal. The resulting "clock" edge is far from ideal. However, the 4017 has a Schmitt-Triggger clock input and the 4017 datasheet states clock input rise time and fall time may be indefinite, so this may work. Although it is imho not good practice to provide such a slow "clock" to a counter. I wouldn't be surprised if the circuit triggers more than once in some cases, e.g. if a load is switched that generates lots of emc noise.

 

[Nanren888]

In summary, it seems that you should consider other circuits or at least compare. Particularly look for ones with a current limit resistor between the sensor and the next transistor, perhaps smoothing on the power supply and maybe what different triggering filtering, conditioning is used.