Pulse dropping circuit.

[Lorthus]

Hello all,

My apologies if I've posted this question in the wrong category.

I'm working on a home project and I'm trying to figure out how to make a circuit that will drop 1 in 3 pulses from 9v input, then deliver the remaining pulses as an output at the input voltage. Think of it as an in-line pulse reducer - where I need to retain 2 out of 3 pulses only. I thought a 555 timer would do the job, but doing a little research I discovered it may not be the best fit. I am quite new to this wonderful world of electronics and would very much appreciate a pointer in the right direction.

Many thanks!

 

[(*steve*)]

So if you got a series of 10 pulses, you'd want to suppress the first, fourth, seventh and tenth?

Is additional power allowed?

Do the pulses have a consistent voltage?

Do the pulses have fast rising and falling edges?

Edit: I'm thinking that a circuit employing a 4017 and an AND gate might do what you want.

 

[BobK]

Is this application in a car? If so there are additional considerations.

Bob

 

[Lorthus]

Hi Steve and Bob - thanks for your replies!

Additional voltage is allowed, yes 1st, 4th, 7th, 10th etc I'd like to drop, the pulse voltage is current, though I'm not sure about how fast the voltage rises and falls - but I'm making a fairly safe assumption in that it must rise and fall very quickly because there are a lot of them per second.

Okay, sorry for the cryptic - I'll apologise and explain. Yes, it's an automotive application. I'm trying to drop 1 in 3 pulses for a tachometer feed. Why didn't I say that at first? Well, I did ask on another forum recently and got ripped a new one for asking about an automotive application. I honestly didn't want the same thing to happen again - hence the cryptic. Again, my apologies. I'm just trying to learn how to do things myself rather then go pay for someone else's work.

 

[AnalogKid]

"deliver the remaining pulses as an output at the input voltage"
"the pulse voltage is current"

I'm struggling with your language, but I think this is it:

You have a continuous pulse train that is the tach signal in a car engine, and you want to reduce the signal to 2/3 of it's original frequency. Is that correct?

If so, not too hard. But you can't just clamp onto a tach wire and cause the pulse frequency to change by a constant ratio as the frequency changes over a range of 10:1 or more. The circuit output will be separate from its input; a separate signal on a separate wire.

One way to discuss pulse signals is in terms of their marks (high signal voltage or logic 1) and spaces (low signal voltage or logic 0). Your original signal is this:
mark space mark space mark space mark space mark space mark space mark space mark space mark space
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - 9 marks, 9 spaces. Mark:space ration is 1:1

One way to the reduce the overall frequency by 1/3 is to inhibit every third mark:
mark space mark space space space mark space mark space space space mark space mark space space space
1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 - 6 marks. Mark:space ratio is 1:3
Each triple-space is seen as a single long space.

Another way is to use more complex logic to create a more even waveform:
mark mark space mark mark space mark mark space mark mark space
1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 - 6 marks. Mark:space ratio is 1:2
Each double mark is seen as a single mark that is not as long as the triple space above,

Which one works best depends on the circuit interpreting the pulses.

ak

 

[Lorthus]

Hi AK,

Thanks for your reply and yes it does make sense. I'll try to explain my wording:

"deliver the remaining pulses as an output at the input voltage" - my original thought was to make "something" that would take the tach information from the computer (what I call its output) and then repeat it but with a third of its signal missing (or dropped if you will). The output from that "something" needs to be at the same voltage as it was when it came in (so the "output" needs to be at the same voltage as the input to the "something" was), so that the voltage to the tach is same as it would be as if the device I'm hoping to construct wasn't there. Ie: Same voltage in and out - just reduced frequency of pulses by 1/3.

"the pulse voltage is current" - meaning the voltage used to create the pulses remains unchanged. It's only the frequency of the pulses that alters. Low revs, low frequency, high revs, high frequency.

Reading your post; let's say the best method turns out to be inhibiting every third mark. Can you suggest an IC to accomplish this, or am I over thinking it? Could I not use a small cap and resistor in parallel to limit the frequency of the signal pulse?

 

[Alec_t]

Here's my design which can be used to raise or lower a pulse frequency, with a simple pot adjustment. Setting the pot at 60% of its travel should give you the required 2/3 lower pulse frequency.

U1 is a hex inverter.
U1a,U1b,R1,R2 are configured as a Schmitt trigger inverter. Q1,Q2 ,Q3 provide a controlled current for charging/discharging C1, and together with the Schmitt inverter form a VCO whose frequency is controlled by the voltage on C2.
The VCO output drives a 'pseudo-monostable' Mono1 (C3,R6,U1d) to give fixed-width brief pulses which, via D2, act to pull down the top end of the pot and hence discharge C5.
The input pulses from the VSS trigger a true monostable circuit Mono2 (U1e,U1f,C4,R7,R8,D4) which outputs brief pulses having the same fixed width as those from Mono1 and which, via D3, act to pull up the bottom end of the pot and hence charge C5.
The pot sets the relative weighting of the pull up and pull down effects and hence the integrated mean voltage on C5. When this voltage crosses the threshold of U1c the gate output flips. U1c output is smoothed by R5,C2 to give the VCO control voltage. By virtue of this feedback, the voltage on C5 stabilises at close to the switching threshold of U1c, i.e. at about Vdd/2, and VCO frequency /VSS Input frequency is set by the pot.


Edit:
The circuit should have a regulated voltage supply and further components may be needed for surge/spike/reverse-voltage protection.

 

[AnalogKid]

Here's my design

Will this design track the input signal without adjustment as its frequency changes over a 10:1 range?

ak

 

[AnalogKid]

"the pulse voltage is current" - meaning the voltage used to create the pulses remains unchanged.

Side note - here in EE land, "current" has a different meaning...

ak

 

[Lorthus]

Alec I deeply appreciate the effort you have gone to and sincerely thank you for providing a hell of a lot more than I was expecting. I didn't realise how much was involved in what I was asking, but in what you have provided I am starting to understand it more so. I hear your cautions and will proceed with them in mind. Thank you very much for your time and expertise!

 

[Lorthus]

Side note - here in EE land, "current" has a different meaning...

ak

That's what I figured Thank you also for your comments and obvious effort. It is very much appreciated.

 

[Alec_t]

Will this design track the input signal without adjustment as its frequency changes over a 10:1 range?

LTspice says 'yes', even a bigger range, providing the fixed pulse-width is appropriate for the input frequency range considered, i.e. is less than the minimum input pulse period.
Here's the .asc if you want to play.

 

[(*steve*)]

Here is my "2 of 3" circuit:



The idea is that the 4017 counts up to 3, and passes the input to the output in 2 of these states.

Note that the 4017 increments on the falling edge of the input pulse to prevent odd glitches.

Schmitt trigger inputs are used to square up the inputs. Significant protection would be needed in an automotive environment (or indeed in many environments) to protect the input.

There is a small chance of a glitch on the falling edge of the third pulse as the 4017 cycles back to "1", however the propagation delay of U3 is likely to be far less than the reset delay of the 4017, and the schmitt trigger inputs of u4 should take care of any runt pulse.

The output pulse length is exactly the same as the input pulse length, the difference in the pulse train is that one in every third positive input pulse is omitted from the output.

I think this literally solves the problem, but I really do like @Alec_t's solution.

 

[(*steve*)]

Here's my design

What is the maximum reverse voltage seen across Q1 and Q2's BE junctions? Would the circuit's operation be badly disrupted if a diode (perhaps schottky) was placed in series with each emitter?

Oh, I'm thinking about a 12V or higher supply. I think you have a 5V supply being used?

 

[Alec_t]

What is the maximum reverse voltage seen across Q1 and Q2's BE junctions?

0.6V, regardless of supply voltage Vdd. Q1 and Q2 protect each other, being wired in inverse-parallel.

Edit:
Running the sim again I see that the two time-constants R(pot)C5 and R5C2 will need tweaking depending on the pulse frequency range to be covered.

 

[(*steve*)]

0.6V, regardless of supply voltage

But if there's 3V across the transistors, then the one with the forward biased BE has 2.3V across the reverse biased BC, and the other with the forward biased BC has 2.3V across the reverse biased BE.

 

[Alec_t]

But if there's 3V across the transistors

Sorry, I was checking the wrong nodes. Good catch. With a 12V supply I see ~6.3 Veb. With a 9V supply ~4.8 Veb. I'll work on a modification.

 

[Alec_t]

Here's the modified circuit. The main change is back-to-back zeners across Q1,Q2 to avoid base-emitter breakdown if the supply voltage is >9V. I also increased various time constants to cope better with lower input pulse frequencies than the original circuit was designed for.