problems with P channel mosfet

[jerk]

Bellow is my circuit design. I am using dual p channel mosfet (FDS4935BZ) to dimm two H7 bulbs using PIC PWM. Since bulbs are connected to the ground in the headlight itself I can only use P channel mosfet. Since P channel mosfet is on when 0V is on the gate I am also using third P channel mosfet to provide 12V from the car's ignition to the gate of dual channel mosfet that actualy controls the current through two H7 bulbs. So when PWM from the PIC is 0 bulbs shoud be dimmed to 0 and when PWM from PIC is 255 bulbs should shine with full brightnes.

Problem is that none of this worked. Bulbs shined at full brightnes even when PWM was set to 50 (20% duty so should be 1V) and also circuit started to overheat. Strange thing is that third mosfet (ZXMP7A17G) that only controls voltage to gate of dual mosfet got burned out.




yellow lines are wire connections on the other side. All the surface mount ICs yellow markings are shown mirrored since they are fliped over on the other side when soldering!

 

[Harald Kapp]

Since P channel mosfet is on when 0V is on the gate

This assumption is wrong. The relevant parameter is the gate-source voltage Vgs which has to be less than the threshold voltage Vth: VGS < Vth for a PMOS because Vgs is negative.
(It's Vgs > Vth for an NMOS as here Vgs is positive).

Assuming an LM2937-5 5 V regulator, the pic's output can only switch between 0 V and 5 V. A gate voltage of 5 V to the single MOSFET with the source tied to +12 V results in Vgs = -7 V. This MOSFET will never be turned off.

Read this thread. It's about driving an N-MOSFET, but the principle behind is the same. This page shows some more examples of similar circuits.

 

[jerk]

Vth for ZXMP7A17G is -1V. So if you said that Vgs<Vth than this is done since Vgs is -7V and this is less than -1V.

Also I did not found any usefull data on the topic you provided. There's to much this way, that way and no straight answers. If someone yould help me round the design so I am able to dimm H7 bulbs using PIC mcu.

Thanks.

 

[Harald Kapp]

So if you said that Vgs<Vth than this is done since Vgs is -7V and this is less than -1V.

O.k., my fault, my sentence was incomplete. It should have read "The relevant parameter is the gate-source voltage Vgs which has to be less than the threshold voltage Vth: VGS < Vth for a PMOS to turn on because Vgs is negative." I was referring to your statement regarding the on-state of the PMOS.
In your circuit, Vgs = -7 V for Vout(pic) = 5 V and Vgs = -12 V for Vout(pic) = 0 V. Therefore in both cases VGS < Vth and the P-MOSFET will always be turned on.

Also I did not found any usefull data on the topic you provided.

Have a look at my post #7 in the link I provided. Replace the NMOS there by a PMOS with the source connected to 12 V, drain to your other MOSFETs. A logic high signal at 'in' will then generate 12 V at the output.

Your 10 kΩ resistor from the single MOSFET to the gates of the pair of MOSFETs is imho too large. It will slow down turn-on of the MOSFETs, thus increasing the power dissipation. Also this resistor together with the 10 kΩ pull-down from the gates to ground creates a voltage divider. The gate voltage will reach only 6 V (1/2*12 V by the divider), therefore Vgs will vary from -12 V to -6 V. These transistors also will never be completely off.
Use a much smaller resistor here, e.g. 100 Ω.

Also turn-off by the 10 kΩ pull-down resistor from the gates to ground may be slow. Watch for excess heating of the MOSFET pair. If it gets hot, replace teh pull-down resistor by a transistor which is controlled by the same signal as the single MOSFET but inversely, such that when the single MOSFET is on, the pull-down transistor is off and vice versa.

Btw: It helps to label your components (R1, R2, Q1, Q2, etc.) this makes describing what to do so much easier than referencing 'the single MOSFET' etc.

 

[jerk]

thanks for your explanation. I am getting there
I have no knowledge of MOSFETs I only thought that only RDSon is important.

so according to your aswers it goes like this:
for PMOS:
on Vgs<Vth
off Vgs>Vth

for NMOS:
on Vgs>Vth
off Vgs<Vth

and in my schematics I have voltage divider in both fets. In first we have actualy only 2.5V to the gate thus it will allways be on since Vgs would be -12V or -9.5V.

On the dual mosfet it will come only 6V so again Vgs will be -6V and Vth=-2V so it will allways be on.

I was thinking if it wouldn't be easier leading 12V to the gate of dual MOSFET and then using NPN to drain the voltage to the ground. Like this:

 

[Audioguru]

Why are your images weird-looking negatives??

The output Mosfets are never turned off.

 

[Harald Kapp]

I was thinking if it wouldn't be easier leading 12V to the gate of dual MOSFET and then using NPN to drain the voltage to the ground. Like this:

This is much better, but the transition fron on to off is controlled by the 10 k resistor from the gates of the pair to 12 V.
A single transistor of the FDS4935BZ has an input capacitance of 1360 pF (datasheet, parameter Ciss). Having two of them in parallel doubles this to 2720 pF.
The time constant of the 10 k resistor and this capacitance is 27 µs - an eternity when it comes to switching times of a transistor.

Have a look at the circuit shown in this blog. The text is in German, but the important thing is the image.
When the signal PWM is high, transistor T2 is on, pulling the gate of MOSFET Q1 low, the output goes to 12 V.
When the signal PWM is low, transistor T2 is off. Transistor T1 is on via the base resistor R1, thus the gate of Q1 is at 12 V. Vgs of Q2 is therefore 0 V and Q2 is off.
Charging and discharging the gate of Q2 is active in both cases and thus fast.