PLL Lock to an Offset Frequency

[hashemi7102]

Hi
I want to design a PLL which must lock to a
frequncy which is a bit different from input frequency.
For example input Frequncy is 8MHz and PLL must synthisize
a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.


How can i do this?

Hanse
Hashemi






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[[email protected]]

Hi
I want to design a PLL which must lock to a
frequncy which is a bit different from input frequency.
For example input Frequncy is 8MHz and PLL must synthisize
a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.


How can i do this?

The obvious answer, which is to design a PLL running at nominally
512MHz and divide this output by 63, 64 or 65, is practicable, but not
all that easy, and doesn't give you exactly the frequencies you want.

The alternative version of this strategy is to run your phase-locked
loop at 8.125MHz and use binary rate multipliers (SN7497 - the HCF4089
isn't fast enough) to steal one or two pulses of every sixty four from
the 8.125MHz clock stream. Unfortunately, the 8.0MHz and 7.875MHz pulse
streams then have rather odd-looking Fourier transforms and would not
be acceptable as clock sources in many applications.

You can get rid of this particular problem by running your PLL at
520MHz and dividing all three output streams by 64, but then you have
to realise your binary rate multiplier in some fast chunk of
programmable logic. This is practicable, but not easy, though it does
have the advantage of giving you exactly the frequencies you want.

The practical way of doing it is to buy two Analog Devices DDS chips,
and use one as the oscillator in a digitally controlled phase-locked
loop, and program the other to track it's output frequency with a fixed
125kHz offset - positive or negative as you choose.

That would be a perfectly practical homework problem, of the sort
modern academics love, because all the difficult and interesting stuff
that make real phase-locked loops such a swine to design and build gets
realised in the digital domain, where everything is much closer to
ideal.

 

[Ian Stirling]

Hi
I want to design a PLL which must lock to a
frequncy which is a bit different from input frequency.
For example input Frequncy is 8MHz and PLL must synthisize
a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.


How can i do this?

Amplitude modulating the input source, and filtering out the carrie?r

 

[Joe McElvenney]

Hi,

I want to design a PLL which must lock to a
frequncy which is a bit different from input frequency.
For example input Frequncy is 8MHz and PLL must synthisize
a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.


How can i do this?

8.000MHz divided by 64 = 0.125MHz

7.875MHz divided by 63 = 0.125MHz

8.125MHz divided by 65 = 0.125MHz


Try a conventional PLL with the appropriate M(64) and N(63/65)
dividers using a couple of down-counters such as the 74HCT40103
and a 4046-like chip (IMHO the 74HCT9046 is the better one).


Cheers - Joe

 

[Fred Bloggs]

I want to design a PLL which must lock to a
frequncy which is a bit different from input frequency.
For example input Frequncy is 8MHz and PLL must synthisize
a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.


How can i do this?

The traditional way is to first determine the increment in offset
frequency say 12.5KHz, then this is 8MHz/N where N=640, set this as the
PLL reference input. Then for an output frequency in the range 7.875MHz
to 8.125MHz, this is a range of multiplication of 630 to 650 of the
12.5KHz reference, which means you place a programmable divider in the
range 630 to 650 in the feedback path from the VCO to the other phase
detector input of the PLL. Then the PLL output can be stepped in that
range of output frequencies with 12.5KHz increments. If you only want
the two frequencies 8+/- 0.125MHZ the set N=64 for a 125KHz reference
frequency, and the divider in the feedback loop switches between
7.875MHz/0.125=63 and 8.125MHz/0.125=65. For a contiuous adjustment is
offset frequency between this to limits, there is the dual modulous PLL,
and this entails, the same setup with the 8MHz divided by 64 driving the
PLL reference input, the programmable counter switching between divide
by 63 and divide by 64 in the feedback path, but now now you mix the
8MHz input with VCO output, low pass filter to extract offset frequency,
frequency detect that with a digital phase/frequency detector against
your offset reference, low pass filter, analog compare that against
null, and use comparator to set PLL programmable feedback divider to /63
if VCO output is high, or to /65 if VCO offset is low. If you need
instantaneous switching then most of this applies but you may need to
switch between to PLLs- is this and FSK application? Your frequencies
are low enough to use a 74HCT4046.

 

[Fred Bloggs]

The traditional way is to first determine the increment in offset
frequency say 12.5KHz, then this is 8MHz/N where N=640, set this as the
PLL reference input. Then for an output frequency in the range 7.875MHz
to 8.125MHz, this is a range of multiplication of 630 to 650 of the
12.5KHz reference, which means you place a programmable divider in the
range 630 to 650 in the feedback path from the VCO to the other phase
detector input of the PLL. Then the PLL output can be stepped in that
range of output frequencies with 12.5KHz increments. If you only want
the two frequencies 8+/- 0.125MHZ the set N=64 for a 125KHz reference
frequency, and the divider in the feedback loop switches between
7.875MHz/0.125=63 and 8.125MHz/0.125=65. For a contiuous adjustment is
offset frequency between this to limits, there is the dual modulous PLL,
and this entails, the same setup with the 8MHz divided by 64 driving the
PLL reference input, the programmable counter switching between divide
by 63 and divide by 64 in the feedback path, but now now you mix the
8MHz input with VCO output, low pass filter to extract offset frequency,
frequency detect that with a digital phase/frequency detector against
your offset reference, low pass filter, analog compare that against
null, and use comparator to set PLL programmable feedback divider to /63
if VCO output is high, or to /65 if VCO offset is low. If you need
instantaneous switching then most of this applies but you may need to
switch between to PLLs- is this and FSK application? Your frequencies
are low enough to use a 74HCT4046.

Unbelievable illiterate post! This is what happens when visualizing
schematics while writing...

 

[John Woodgate]

I read in sci.electronics.design that Fred Bloggs <[email protected]>

Unbelievable illiterate post! This is what happens when visualizing
schematics while writing...

Don't be too hard on yourself. It improves a lot with a few paragraphs
applied. The typos become more easily interpreted, too.

 

[Jim Thompson]

Hi
I want to design a PLL which must lock to a
frequncy which is a bit different from input frequency.
For example input Frequncy is 8MHz and PLL must synthisize
a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.


How can i do this?

Hanse
Hashemi

Divide 8MHz by 64 for reference input (125KHz) then use div63 or div65
in the feedback.

OR:

Use a single-sideband mixer to mix 125KHz with 8MHz.

...Jim Thompson

 

[[email protected]]

<snip>

Nice scheme - much better than my first two proposals, but a vile
description.

Your idea seems to be that you have two voltage controlled oscillators,
in two linked phase locked loops. The first oscillator is running at
8MHz, which the first phase-locked loop locks directly to the 8MHz
input. The output from the first VCO is also divided down by 640 to
provide a 12.5kHz reference waveform, which happens to be phase-locked
back to the 8MHz input.

You then set up the second voltage-controlled oscillator to run at a
different frequency - say 7.875MHz = which you divide down by 630, to
provide a second nominally 12.5kHz signal.

You then use a second phase sensitive detector to compare the two
12.5kHz signals, and drive the second - nominally 7.875MHz - VCO to
force the two 12.5kHz outputs into lock. This second phase locked loop
thus indirectly synchronises the 7.875MHz oscillator to the 8MHz input.

You frequency difference is 1/64th of the input frequency, rather than
an absolute 125kHz, but in all other respects this strikes me as a
perfect solution.

Not as easy to realise as my third solution - a digital phase locked
loop built around a pair of DDS chips, which could deliver an absolute
frequency offset, if that was what you wanted, but probably much
cheaper.

 

[Phil Hobbs]

Divide 8MHz by 64 for reference input (125KHz) then use div63 or div65
in the feedback.

OR:

Use a single-sideband mixer to mix 125KHz with 8MHz.

...Jim Thompson

If you use a frequency-phase detector or other very asymmetric PD, you
don't even have to use an SSB mixer, because the unwanted null is
unstable. On each sideband, one null is unstable because of the sign of
the loop gain. On both sidebands, the null at +- pi is unstable because
of huge loop gain. Only one of the four nulls is stable.

Cheers,

Phil Hobbs

 

[Tim Wescott]

Divide 8MHz by 64 for reference input (125KHz) then use div63 or div65
in the feedback.

OR:

Use a single-sideband mixer to mix 125KHz with 8MHz.

...Jim Thompson

Assuming a low-noise input signal a 3-state phase/frequency detector,
like the phase detector II in the 4046 or that ELC part that Jim will
shortly tell you about makes a good alternative.

Mix your oscillator signal with your input; the "up" (or "down") pin on
the phase detector will pulse with energy at f_osc + f_signal and f_osc
- f_signal. The nice thing is that only _one_ pin will pulse; the other
one will stay steady. If your oscillator frequency is on the wrong side
of your signal the wrong pin will pulse and the right pin will stay
steady, so you'll be able to drive your loop in the correct direction.
Low-pass filter the appropriate pin, square it up with a comparator, and
apply it to another suitable phase detector with 125kHz as a reference.

If you use the 4046 for this both the "up" and "down" signals are
brought out to the same pin (13). You'll have to pull pin 13 high or
low with a resistor and square it up with an inverter before you filter it.

 

[Frank Bemelman]

Your idea seems to be that you have two voltage controlled oscillators,
in two linked phase locked loops. The first oscillator is running at
8MHz, which the first phase-locked loop locks directly to the 8MHz
input. The output from the first VCO is also divided down by 640 to
provide a 12.5kHz reference waveform, which happens to be phase-locked
back to the 8MHz input.

Why would you want to do that? Divide the 8MHz by 640 and use that as
your new reference.

You frequency difference is 1/64th of the input frequency, rather than
an absolute 125kHz, but in all other respects this strikes me as a
perfect solution.

We only know that the input frequency is 8MHz. That's as absolute
as it comes, and 1/64th of it is therefore an absolute 125KHz.

[snip]

 

[Jim Thompson]

If you use a frequency-phase detector or other very asymmetric PD,

Huh? A PFD isn't asymmetric.

Reread my first example: 65/64*8MHz = 8.125MHz, 63/64*8MHz = 7.875MHz

you
don't even have to use an SSB mixer, because the unwanted null is
unstable. On each sideband, one null is unstable because of the sign of
the loop gain. On both sidebands, the null at +- pi is unstable because
of huge loop gain. Only one of the four nulls is stable.

Cheers,

Phil Hobbs

My second example, elaborating: 8MHz/64 = 125KHz, then MIX in an SSB
mixer to get the +/- desired. No PLL needed, just some phase shifters
;-)

...Jim Thompson

 

[Tim Wescott]

On Fri, 14 Oct 2005 11:49:51 -0400, Phil Hobbs -snip-



Huh? A PFD isn't asymmetric.

I think he means that a PFD will give output on only one pin when the
frequencies differ -- you have to get close to lock or otherwise have
the two signal frequencies swimming around each other before both pins
become active.

-snip again-

My second example, elaborating: 8MHz/64 = 125KHz, then MIX in an SSB
mixer to get the +/- desired. No PLL needed, just some phase shifters
;-)

...Jim Thompson

True, but image-reject mixers can be tricky and filtering methods aren't
very frequency-agile. If you want both the input frequency and the
offset to vary by much it would be easier to do it with phase-frequency
detection.

 

[Phil Hobbs]

Huh? A PFD isn't asymmetric.

Reread my first example: 65/64*8MHz = 8.125MHz, 63/64*8MHz = 7.875MHz






My second example, elaborating: 8MHz/64 = 125KHz, then MIX in an SSB
mixer to get the +/- desired. No PLL needed, just some phase shifters
;-)

...Jim Thompson

Of course it's asymmetric. The voltage vs phase plot is a sawtooth.

Cheers,

Phil Hobbs

 

[Jim Thompson]

I think he means that a PFD will give output on only one pin when the
frequencies differ -- you have to get close to lock or otherwise have
the two signal frequencies swimming around each other before both pins
become active.

-snip again-


True, but image-reject mixers can be tricky and filtering methods aren't
very frequency-agile. If you want both the input frequency and the
offset to vary by much it would be easier to do it with phase-frequency
detection.

True, but the OP was (presumably) a fixed input frequency and (again
presumably) selectable output frequency.

I did one this past year for a WiFi chip (924MHz/1188MHz) using SSB,
which is what the customer wanted. But I think, in retrospect, I'd
talk the customer into a PLL next time around. I think it'd take up
less silicon real estate.

...Jim Thompson

 

[Jim Thompson]

Of course it's asymmetric. The voltage vs phase plot is a sawtooth.

Cheers,

Phil Hobbs

Not on either side of zero phase it isn't... it's linear thru zero.
With a PFD you could care less about ±pi.

...Jim Thompson

 

[Tim Wescott]

Jim Thompson wrote:

-snip-

I did one this past year for a WiFi chip (924MHz/1188MHz) using SSB,
which is what the customer wanted. But I think, in retrospect, I'd
talk the customer into a PLL next time around. I think it'd take up
less silicon real estate.

...Jim Thompson

Customer: "I want you to build me a big gun, to be lined up with my
right thigh per this here drawing and fired into the ground".

You: "You want to shoot yourself in the foot?!?"

Customer: "No, I want to quickly and efficiently make holes in the
ground. Geez."

You: "But your foot is in the way! Look at your own drawing!"

Customer: "Don't be a barrier to progress! Just build the damn thing
and bill me!"

You: "Well, if you insist..."

(later)

Customer: "Hey! Your equipment is a piece of xxxx and my foot hurts
really bad!"

This is worse when your customer is also your boss, which is why I'm now
a consultant...

 

[Jim Thompson]

[snip]

Customer: "Hey! Your equipment is a piece of xxxx and my foot hurts
really bad!"

This is worse when your customer is also your boss, which is why I'm now
a consultant...

I decided that in 1973 ;-)

...Jim Thompson

 

[Phil Hobbs]

Not on either side of zero phase it isn't... it's linear thru zero.
With a PFD you could care less about ±pi.

...Jim Thompson

Jim, with all due respect, you need to think about what I wrote in my
original post. The sign of the loop gain is opposite for USB and LSB
for a given PD null, i.e. if you use an XOR or a diode mixer whose nulls
are at quadrature, if the loop wants to lock up at +pi/2 on USB, it'll
lock up at -pi/2 on LSB. With a PFD, one sideband will have the right
sign of loop gain to lock up at 0, where (as you point out) everything
is copacetic.

The point I was making in my original post is that the other sideband
will have to try locking up at +- pi, where there's a ruddy great
cliff--its PD gain there is like Vdd /2*pi*(f_0*t_PD), i.e. something
like 500 times larger than the other null. Of course it's noisy and
possibly metastable there, but the point is that the loop gain is
_huge_, so no lock will occur there. Thus with a tiny bit of
acquisition aiding, e.g. 2 resistors and a cap in positive FB around the
loop amplifier, you can make a reliable lock to one sideband and not
the other, _without_needing_a_SSB_mixer_.

Cheers,

Phil Hobbs