Pipelining and modified datapath

[fred9527]

Hi

I encounter this question on pipelining, and I have seen the answer too. I just have no idea why this whole circuit should be pipelined like this. Please kindly gimme some guidance. Thank you very much.

Here is the question.







And here is the answer.

 

[Merlin3189]

You probably need to think about how a ripple adder works (or look it up.)

After the data inputs are valid, how long before the Co from the first adder is valid?

For the second adder, are ALL its inputs valid at the same time as the first adder? So when do they become valid? And when do its outputs become valid?

Then for the third and fourth adders?

So when are all 16 outputs valid?

So what is the shortest clock period (between writing valid data to the adder and reading a valid result?)

Now with your "pipelined" circuit, what is the shortest clock period between clocking the flip-flops?