pierce cmos oscillator question

[RBola35618]

In designing a pierce cmos oscillator using a cmos inverter with a quartz
crystal and loading capcitor c1 and c2, is there a design rule regarding the
amount of gain margin needed to insure that oscillator starts properly?

I know that an oscillator is suppose to satify the Barkhusen criteria which
says the gain of the inverter time the gain of the feedback must exceed 1 and
that the feedback has to be in phase or 360 degress.

Is there a general rule of thumb regarding the open loop gain and phase margin
test?

In looking at crytal manufacturers application note, I have run into what is
call the negative resistance test in which a resistor is inserted in series
with the crystal and the resistance is increased until the oscillator stop
working. Using this methode, the rule of thumb that I have seen is the
negative resistacnce is suppose to be at least 5 to 10 time the equivalent
series resistance of the crystal.

Which bring me back to, is there a general desgin rule when using the open loop
gain and phase margin test .

Robert

 

[Jim Thompson]

In designing a pierce cmos oscillator using a cmos inverter with a quartz
crystal and loading capcitor c1 and c2, is there a design rule regarding the
amount of gain margin needed to insure that oscillator starts properly?

I know that an oscillator is suppose to satify the Barkhusen criteria which
says the gain of the inverter time the gain of the feedback must exceed 1 and
that the feedback has to be in phase or 360 degress.

Is there a general rule of thumb regarding the open loop gain and phase margin
test?

In looking at crytal manufacturers application note, I have run into what is
call the negative resistance test in which a resistor is inserted in series
with the crystal and the resistance is increased until the oscillator stop
working. Using this methode, the rule of thumb that I have seen is the
negative resistacnce is suppose to be at least 5 to 10 time the equivalent
series resistance of the crystal.

Which bring me back to, is there a general desgin rule when using the open loop
gain and phase margin test .

Robert

The rule-of-thumb I use:

Load crystal with capacitors per manufacturer's specifications (2*CL
on each end to ground).

Use a series R equal to R = 1/(pi*fx*CL)

I've *never* had an oscillator of this sort fail to start.

If you're using PSpice, go to my website and download the Part
"LoopGain". This implements Middlebrook's two-step gain/phase
analysis and is impedance independent. (This *may* be implementable
in other Spice's if a part can convey a .STEP operation.)

...Jim Thompson

 

[Jim Thompson]

On Thu, 08 Jan 2004 19:39:54 -0700, Jim Thompson

[snip]

Use a series R equal to R = 1/(pi*fx*CL)

[snip]

Oooops! Typo! Make that R = 1/(4*pi*fx*CL)

...Jim Thompson

 

[RBola35618]

Hi James,

Can you clarify how the resistor is wired up. Is the resistor suppose to be in
series with the crystal ?
(resistor between crystal and (output of invertal and C1)

or in series with the output of inverter (resistor between invertor and (C1 and
crystal ). Used In a damping configuration?.

I hope I made some sense.

Robert Bolanos

 

[Jim Thompson]

Hi James,

Can you clarify how the resistor is wired up. Is the resistor suppose to be in
series with the crystal ?
(resistor between crystal and (output of invertal and C1)

or in series with the output of inverter (resistor between invertor and (C1 and
crystal ). Used In a damping configuration?.

I hope I made some sense.

Robert Bolanos

Between output of inverter and crystal/first-capacitor junction.

It's purpose is two-fold: phase-shift and drive-limiting.

...Jim Thompson

 

[Tim Shoppa]

In designing a pierce cmos oscillator using a cmos inverter with a quartz
crystal and loading capcitor c1 and c2, is there a design rule regarding the
amount of gain margin needed to insure that oscillator starts properly?

Yes, but in the end it doesn't do you that much good. The reason is that
the CMOS inverters you use in the oscillator will vary radically in gain
over typical operating Vcc, temperature extremes and part-to-part
variations.

Not only is gain vs all those factors important, but the dynamic
output impedance of the inverters at the operating frequencies can be
important (especially if the capacitors are more than a few pF
and the frequencies are high).

Actual construction matters too, as in some cases the stray capacitances
are appreciable compared to the loading capacitors.

In a few cases you can get CMOS parts with guaranteed parameters to the
extremes. Otherwise you just build in a large factor of safety margin,
such that the oscillator doesn't get overdriven but still starts and
runs reliably.

That doesn't mean that careful analysis takes a back seat to testing.
Just that the relevant AC parameters have to be determined by testing
as they are rarely on datasheets. Sometimes they are in SPICE models
but these aren't usually aimed towards the linear region.

Tim.

 

[Tony Williams]

In designing a pierce cmos oscillator using a cmos inverter with
a quartz crystal and loading capcitor c1 and c2, is there a
design rule regarding the amount of gain margin needed to insure
that oscillator starts properly?

[snip]

Application note AN97090 from Philips Semiconductors gives a
detailed mathematical explanation of the Pierce CMOS gate
oscillator and the conditions required for starting.
It's about a 2meg PDF from their site, well worth obtaining.
Umm.... I forget the exact URL unfortunately.

 

[Jim Thompson]

In designing a pierce cmos oscillator using a cmos inverter with
a quartz crystal and loading capcitor c1 and c2, is there a
design rule regarding the amount of gain margin needed to insure
that oscillator starts properly?

[snip]

Application note AN97090 from Philips Semiconductors gives a
detailed mathematical explanation of the Pierce CMOS gate
oscillator and the conditions required for starting.
It's about a 2meg PDF from their site, well worth obtaining.
Umm.... I forget the exact URL unfortunately.

http://www.semiconductors.philips.com/acrobat/applicationnotes/AN97090_1.pdf

...Jim Thompson

 

[Tony Williams]

http://www.semiconductors.philips.com/acrobat/applicationnotes/AN97 090_1.pdf

Thanks Jim.

 

[RBola35618]

Thanks for the appilcation notes. The info is very usefull.

Robert Bolanos