Hi everybody
How are you doing today!
I have several questions related to Phase lock loop. I already
implemented a layout for a charge pump phase lock loop. It is working
fine. I really want to do the process variation on it for my master
thesis and however I am stuck now....
The first question is how to get the simulation result on DC gain. I
know how to calculate the DC gain with analytical results (get the
transfer function and make the s = 0). What I want to do is to vary a
capacitor or resistor's value and get the experimental results on DC
gain using Hspice and see if the DC gain is changing in the direction
predicted by the analytical results. However, I do not know what to
measure to get the DC gain with hspice. I mean I do not know what value
I should measure to get the DC gain. I tried to give a DC reference
signal, but that does not seem right.
The second thing is that I want to find some analytical results giving
the relationship between the any transistor sizing and the any loop
characteristics. For example, the charge pump's currency is related
to the transistor size. I think the currency is also related to the
loop's locking time, locking range, etc. If I can get some analytical
results on that, that will be very wonderful! Of course, the loop
characteristic has to be some thing that I can measure from hspice
simulation results.
Now I just have the equation for the first order xor pll from my text
book. That is a super simple topology and even does not have charge
pump. I cannot use that since it is not the same as my topology and the
topology is too simple - my advisor said.
Could any body give me some hints on the analytical results of this
type for a traditional phase lock loop? Any reference or any ideas?
Thank a lot a lot if anybody can help me out.
My email address is [email protected]. If you have some
ideas and you do not mind sharing your ideas with me, kindly please
drop me a line. If you are in US too and you prefer talking directly,
please leave me a number or I can give you my number.
Thank you very much again!
Have a nice day!
How are you doing today!
I have several questions related to Phase lock loop. I already
implemented a layout for a charge pump phase lock loop. It is working
fine. I really want to do the process variation on it for my master
thesis and however I am stuck now....
The first question is how to get the simulation result on DC gain. I
know how to calculate the DC gain with analytical results (get the
transfer function and make the s = 0). What I want to do is to vary a
capacitor or resistor's value and get the experimental results on DC
gain using Hspice and see if the DC gain is changing in the direction
predicted by the analytical results. However, I do not know what to
measure to get the DC gain with hspice. I mean I do not know what value
I should measure to get the DC gain. I tried to give a DC reference
signal, but that does not seem right.
The second thing is that I want to find some analytical results giving
the relationship between the any transistor sizing and the any loop
characteristics. For example, the charge pump's currency is related
to the transistor size. I think the currency is also related to the
loop's locking time, locking range, etc. If I can get some analytical
results on that, that will be very wonderful! Of course, the loop
characteristic has to be some thing that I can measure from hspice
simulation results.
Now I just have the equation for the first order xor pll from my text
book. That is a super simple topology and even does not have charge
pump. I cannot use that since it is not the same as my topology and the
topology is too simple - my advisor said.
Could any body give me some hints on the analytical results of this
type for a traditional phase lock loop? Any reference or any ideas?
Thank a lot a lot if anybody can help me out.
My email address is [email protected]. If you have some
ideas and you do not mind sharing your ideas with me, kindly please
drop me a line. If you are in US too and you prefer talking directly,
please leave me a number or I can give you my number.
Thank you very much again!
Have a nice day!
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