For the fast tour ....
Without knowing the details of the reference design you saw, the two
frequency ranges (at the input) of interest of any PLL are:
Lock range (Acquisition range)
Hold-in range
[Other frequencies of interest in a PLL include the phase rate (the
rate at which the input frequency can change) the PLL can follow and
loop frequency (the filter characteristics of the loop filter in the
frequency domain) - these two are closely related in terms of PLL
performance].
At the output we care about the ouput VCO range (which may be directly
fed back or may be sent through dividers as is done in frequency
synthesis).
Both *input* ranges are a function of the VCO (the VCO Fout/Vin
function determines the output frequency range of the VCO), the phase
detector and the loop filter (and divders if present), but typically
Hold-in is wider than lock, although not always.
To address your questions:
If the frequency is higher or lower than the acquisiton range (assuming
it is unlocked),
PLLs will do one of a number of things, depending on whether there is a
signal present or not, and whether it is within the lock/hold-in range
of the input
a. Sweep across their frequency range (Sawtooth applied to VCO
V[control] as the phase detector gives a varying output (common if
F[in] is outside the lock range of the PLL, but depends on the
characteristics of the phase detector)
b. Sit at a single frequency (except for jitter) - common for many PLLs
in the absence of a signal.
As to 'How does it know the signal is within that range' - the range of
frequencies a PLL can cover is determined by the overall
characteristics as noted above.
Cheers
PeteS
