PFD for John Larkin

[Jim Thompson]

John, See...

Newsgroups: alt.binaries.schematics.electronic
Subject: In Reply to a PFD Question on S.E.D - DD-PFD.pdf
Message-ID: <[email protected]>

...Jim Thompson

 

[John Larkin]

John, See...

Newsgroups: alt.binaries.schematics.electronic
Subject: In Reply to a PFD Question on S.E.D - DD-PFD.pdf
Message-ID: <[email protected]>

...Jim Thompson

Most cool. Thanks. This will implement in one or two Xilinx CLBs, with
around 100 ps max prop delay. Looks like the pumpup and pumpdown can
overlap a bit, which is good.

Interesting: if the fpga logic is too fast, the overlap may go away
because the tristate charge-pump outputs can't respond fast enough to
very skinny pump pulses. Dunno, will consider. One could always add a
little delay into the ff resets path, I guess, or place the r-s latch
far away from the flipflops on the chip.

We may need to be careful that the compiler doesn't "improve" it for
us.

John

 

[Rob Gaddi]

Most cool. Thanks. This will implement in one or two Xilinx CLBs, with
around 100 ps max prop delay. Looks like the pumpup and pumpdown can
overlap a bit, which is good.

Interesting: if the fpga logic is too fast, the overlap may go away
because the tristate charge-pump outputs can't respond fast enough to
very skinny pump pulses. Dunno, will consider. One could always add a
little delay into the ff resets path, I guess, or place the r-s latch
far away from the flipflops on the chip.

We may need to be careful that the compiler doesn't "improve" it for
us.

John

Probably a dumb question, but could you just save the external VCXO and
use one of the onboard DCMs instead?

 

[John Larkin]

Probably a dumb question, but could you just save the external VCXO and
use one of the onboard DCMs instead?

The VCXO is the main clock for the whole board. The product will be a
time-delay generator, and we'll furnish a cheapish surfmount crystal
oscillator as the timebase. If the customer wants it to be real
accurate, or wants to use more than one unit and still have the delays
match, he can use a very good external 10 MHz clock, or sync two boxes
to each other. This board will be *very* dense so we want a minimalist
phaselock system, with the guts inside the FPGA.

Hmmm, what does Jim's circuit do if F1 <> F2? The 4046 or 9901 pd's
will always drive the vco towards lock regardless of how far it's off
and how narrow the loop filter, which a simple pd won't do. That's why
they're called frequency/phase detectors.

(hey, got my 'trippin' email?)

John

 

[Mike Monett]

John Larkin wrote:

[...]

Hmmm, what does Jim's circuit do if F1 <> F2? The 4046 or 9901 pd's
will always drive the vco towards lock regardless of how far it's off
and how narrow the loop filter, which a simple pd won't do. That's why
they're called frequency/phase detectors.

John

I haven't seen Jim's pfd, but if it's a standard dual-D with nand
feedback, it's a standard frequency/phase detector and operates the same
way. If you need confirmation, here's one implemented in ecl. The pfd is
elements 24, 26, 28, and 58 in

http://www3.sympatico.ca/add.automation/patents/287f2d4a.gif

the timing diagram is included in

http://www3.sympatico.ca/add.automation/patents/287f1101.gif

Deadband may be a problem with the fast logic you described, especially
if you are limited in the amount of delay you can add in the feedback
path to permit locking at high clock frequencies.

If you use resistive coupling to an error amplifier, splitting the
resistors in half and adding a small bypass to ground may slow the pulses
down enough so the op amp can follow phase errors through zero. This
assumes you use a pure integrator as a feedback filter around the op amp,
per your previous posts.

Mike Monett