PCB footprint question?

[jackorocko]

Can anyone look at my footprint that created for the LMD18245. I just need a set of experienced eyes that can maybe point me to anything I might have done wrong.

Datasheet: http://www.ti.com/lit/ds/symlink/lmd18245.pdf

Pin 1 - Pin 15 = .700mils
center to center on adjacent holes in same row is .100mils
center to center on row spacing is .200mils
second row is offset by .050mils
hole circumference is .032mils
pad circumference is .060mils

I am wondering if I need larger pads since some of these pins will be supplying up to 3A @ 50V. Is there any sort of rule on size of pads/traces for power requirements? I know there has to be, but can anyone point me to a source of relevant information?

 

[GonzoEngineer]

Hi Jackorocko,

I don't know about relevant sources, but I have been designing PCB boards for almost forty year, and here are my opinions.

I would use 50 mill traces for the power, ground and output traces. With a standard 2 oz. copper board, that will be just fine.

Pay particular attention to the large cap on the Vcc. It is there to supply the pulsed power for the outputs. Make sure it is a low ESR capacitor. because if you use something cheap you are going to see a lot of noise.

Make the power and ground traces for the IC come directly from the power source into the board, and don't let any other circuits try to share the same ground or power traces.

From the data sheet, you have to assume that the odd pins are the ones bent forward, but I would double check when you get the part in your hands.

Other than that, you look good to go.

 

[OLIVE2222]

Hi jackorocko,

A rule of thumb is to have the pad diameter around 2 time the hole diameter, the current is not really limited here thanks to the solder join.
for the tracks dimenssioning you can have a look here:

http://www.desmith.net/NMdS/Electronics/TraceWidth.html

National provide CAD libraries, don't know if it's match your CAD package.

http://www.national.com/cad/

through hole components footprints are not to sensitive assuming all the pin spacing are respected. just take care about the heat sink pad width if you place the component on the PCB edge (for heatsink mounting purpose). You can also print the footprint at 1/1 scale and check with the component. Also better to bold it before soldering to avoid stress on the pins.

Olivier

 

[jackorocko]

Ok, I am getting really frustrated with this PCB layout stuff. I tried using a Ground plane to connect all my grounds, but what a crap shoot that is. I always seem to be breaking my ground plane, which would force me to connect the ground plane on bottom with a trace on top. This seems unacceptable to me.

Also, I kinda get the impression that I should be using two different grounds. A signal ground and a power ground. Does this make any sense? Please someone advice me, I have spent one day to many already on this layout. Seems easier then it looks is all I am gonna say.

 

[jackorocko]

Alright, well I think I finally did it. 3x2" board. The only question I have is should I separate the PGND from the SGND? PGND being the 50mil traces.

edit: Instead of trying to set a ground plane on the SGND like an idiot for thermal dissipation, I decided to attach it to PGND (GNDA in schematic). This makes more sense since this is where most of the power and heat will be produced. My second picture is Rev2 and this is what I plan on keeping. Hopefully someone can look it over and let me know of any glaringly obvious mistakes.

 

[OLIVE2222]

Hi,


However it's probably electrically OK it smell auto-routing, you can improve it by routing the board manually as the density is low.
By placing the main tracks part on the bottom layer you can free up the top for ground purpose. It's also easier to work with when tracks are accessible.



Clean the "mess" around RV1
made direct connection on P2-1, P4-1
center the track under P4
avoid track close to C11-2,C6-1, C2-1
made direct connection on JP1-2&JP2-2
no decoupling cap on the PIC
increase +5V track width
Avoid 45° angles like on C2, C6 -1 it's an "acid trap"
made direct pad connection avoid thinks like on U1-12
You can maybe leave the crystal footprint even if not mounted
You can maybe add pads on unused PIC pin's
You can maybe add a small prototyping area
You can maybe add a fuses on drivers
You can maybe add a reverse polarity protection

Olivier

 

[jackorocko]

Ok, few more details please.

made direct connection on P2-1, P4-1
made direct connection on JP1-2&JP2-2

What do you means by this? They are connected. P4-1 can't be any more direct. Lost you here.

avoid track close to C11-2,C6-1, C2-1

Is it better to avoid the GND or VCC on capacitors and what is excepted as to close?

increase +5V track width

20mils?

no decoupling cap on the PIC

I would like to take credit for this design, but I can't. Where does the decoupling cap need to go? This design is supposed to work very well in its present state, I am just trying to re-route the PCB design to bring down my cost. I so far decreased my cost by ~$30 bucks over the original design.

Also, what is the thinking with "VIA's". I personally try to avoid these like the plague.

 

[jackorocko]

Olivier, I tried it again this time manually doing all the traces. I did what you said and did the bulk of my traces on the bottom. Once I ran out of avenues, I jumped to the top to finish off the connections. I have (2) GND planes. One on the bottom for GNDA and one on the top for GND. I increased the 5V traces to 10mils. I have zero 45 degree angles and I tried to come straight off (90 degrees) to every connection before making a turn.

C2 is still a little problem area, do you think I need more distance between my signal traces and the C2-1 and C2-2 connections?

 

[OLIVE2222]

OK Jackorocko, looks cleaner now!

You can finalize the grounds filings as it:

Reduce the isolation and/or via diameter a bit to allow filling between PIC and drivers pads.
Avoid paralleling track to closely like RB7, +5V and RB6 tracks to allow the ground finding is way. You can move above the 10K resistors and the PIC a bit to allow the AGND filling on the board bottom. You can move a bit bottom/left the 10K R between U1 and U3 to allow filling on the board top. others optimizations like this should allow an almost GND filled PCB.


About my previous post:

made direct connection on P2-1, P4-1 the tracks are not aligned with the hole center, the green one as an ugly right angle the 20k one in not directly connected to the pad and the large one is top shifted a bit.

avoid track close to C11-2,C6-1, C2-1
Looks better to regularly space the track and the pads, can ease the gnd filling between track and easier to (homemade) manufacture.

It's a good practice that add decoupling cap directly on logic VCC pin's , the closer the better.

Via are very helpful if the PCB is professionally made, i agree that's is a pain for homemade PCB's.

Olivier

 

[jackorocko]

Looks good to me now. I added in the ztt-resonator and added a decoupling cap of 1uF across the pic's power supply. Also added a few drill holes to mount the pcb. Cleared the traces away from C2 and cleaned up the component references, all are visible with parts soldered in.

I didn't mess to much with the ground planes. Not sure it matters that much.

 

[OLIVE2222]

it' s OK, you can maybe just move the decoupling cap close to the PIC pin 14.

Olivier