Not sure about PIC ICSP Spec

[Jon Slaughter]

I'm having a hard time figuring out what this spec means

http://www.semiconductorstore.com/pdf/newsite/microchip/PIC24FJ128GA006_PG.PDF

On Page 21 there is a Note 1 in 4.2.1,

"Coming out of Reset, the first 4-bit control
code is always forced to SIX and a forced
NOP instruction is executed by the CPU.
Three additional PGCx clocks are
needed on start-up, thereby resulting in a
7-bit SIX command instead of the normal
4-bit SIX command. After the forced SIX
is clocked in, ICSP operation resumes as
normal (the next 24 clock cycles load the
first instruction word to the CPU)."

Ok, I see that essentially when it comes out of a reset there is a special
case. But I do not know how to use this special case. What does it really
mean comming out of a reset? Is this every time the MCLR pin is used to
reset the pic?

What I have got is some code that executes a normal six serial execution
instruction(without the extra 3 bits) and I can also enter ICSP mode. (Well,
I'm using LED's to check the timings and stuff and slowing them down and
everything looks good)

I'm just not sure when I'm suppose to use this special instruction? I figure
I would have to use it right after I enter ICSP mode given on page 22 but I
really don't have a good idea about it.

Also in the timing diagram they show 4 + 24 + 4 bits or for the special code
7 + 24 + 4. Is the last 4, where it says "Execute 24-bit Instruction..."
part of the first 4 for a new command. It says right above Note 1 that it
simultaneously executes the 24-bit instruction previously clocked in while
recieving the next control code. This makes it sound as if those 4 bits are
part of the next instruction(so if I wanted to use the REGOUT control code I
would actually clock in 0001 after the 24-bit instruction?)?


Any ideas? I think once I solve these I can then attempt to program a chip.

Thanks,
Jon

 

[Jon Slaughter]

Another "strange" thing that came up is in figure 4-4: Entering ICSP Mode.
After the key sequence has been clocked in the MCLR must go from low to high
and there is a timing of P17 which says max of 100ns. In the timing guide it
says that P17 is "MCLR downarrow to Vdd downarrow". It makes no sense to me
what this means. Seems like they mean Vih instead of Vdd but I have no clue.
It also seems that the way the timing is showing that MCLR must go high
within 100ns after the last data bit of the key squence is clocked in. This
doesn't sound right? (If so then I'm screwed cause it will be several us's
before I can change the MCLR from the last bit unless I change it with the
clock itself(so make P17 = 0))

Can anyone understand what the heck there talking about? Maybe its me but
this datashit doesn't make much sense ;/

Thanks,
Jon

 

[neon]

look at the pulse diagrams it tells you at start up master clear must go up to clear before programming because mclr is a bar function.