Noob question about the bitscope schematic

[Monty Hall]

I was looking @ the analog input section of the bitscope
(http://www.bitscope.com/design/hardware/analog/). For a single input
channel, what do the 2 JFETS and BJT do? Why can't this be eliminated and
connected directly to the op-amp? If not, why is the BJT required? It
looks like it's behaving like a diode, why not just use a diode? It
appears that the lower JFET & resistor combination is a current source w/ a
fixed gate source (vgs). The upper JFET should have the same vgs. If
anybody could tell me what the JFET/BJT section before the op-amp does,
would appreciate.

Monty

 

[David L. Jones]

I was looking @ the analog input section of the bitscope
(http://www.bitscope.com/design/hardware/analog/). For a single input
channel, what do the 2 JFETS and BJT do? Why can't this be eliminated and
connected directly to the op-amp? If not, why is the BJT required? It
looks like it's behaving like a diode, why not just use a diode? It
appears that the lower JFET & resistor combination is a current source w/ a
fixed gate source (vgs). The upper JFET should have the same vgs. If
anybody could tell me what the JFET/BJT section before the op-amp does,
would appreciate.

Monty

The JFET is a high impedance input stage. This is required on a CRO in
order to get the standard 1Mohm input impedance provided by R26. The
opamp does not have high enough input impedance to do this, if it did,
then yes, you could connect direct to the opamp.

This is a common circuit for CRO front ends. Q3 is usually a resistor
in the basic implementation.
Q3, RV3 and C35 could be removed, but the FETs would have to be be
extremely well matched electrically and thermally to ensure no offset.

Dave

 

[David L. Jones]

The JFET is a high impedance input stage. This is required on a CRO in
order to get the standard 1Mohm input impedance provided by R26. The
opamp does not have high enough input impedance to do this, if it did,
then yes, you could connect direct to the opamp.

This is a common circuit for CRO front ends. Q3 is usually a resistor
in the basic implementation.
Q3, RV3 and C35 could be removed, but the FETs would have to be be
extremely well matched electrically and thermally to ensure no offset.

Dave

I forget to add that, yes Q3 could be replaced by a diode.
But either way I can't see why Q3 is needed, it will in fact add some
temperature dependency to the DC offset, that's bad.
Replacing Q3 with a resistor (the traditional circuit topology) ensures
no temperature related DC offset (assuming RV3 has the same tempco).
But even if they are different tempcos it's probably going to be
negligable. Using Q3 on the other hand will I suspect add quite
substantial DC offset with temperature change.

Dave

 

[Phil Allison]

"David L. Jones"

This is a common circuit for CRO front ends. Q3 is usually a resistor
in the basic implementation.
Q3, RV3 and C35 could be removed, but the FETs would have to be be
extremely well matched electrically and thermally to ensure no offset.

** Dunno what drugs Dave is on - or not on - but the circuit is NOT a
differential pair of FETS so his remarks re offset are irrelevant.

The trim pot merely sets the current flowing through Q7 and hence also Q6.

When that current level is such that the *bias* voltage between the gate and
source of Q6 is *equal* to the Vbe of Q3, then the output rests at zero
volts.




......... Phil

 

[Phil Allison]

"David L. Jones"

Using Q3 on the other hand will I suspect add quite
substantial DC offset with temperature change.

** The offset and offset drift are already completely screwed by the use of
1N4148s for D8 and D9 which are NOT low leakage types.




........ Phil

 

[David L. Jones]

"David L. Jones"


** Dunno what drugs Dave is on - or not on - but the circuit is NOT a
differential pair of FETS so his remarks re offset are irrelevant.

I was referring to the more basic (standard) circuit that has no
resistors (or Q3 for that matter), just the two FETs. In this case the
two FETs must be matched in order not to get any DC offset on the
output.
Adding the resistors (or VR3 + Q3) allows the use of non-matched FETs,
but trimming is required for the DC offset.

Adding the transistor Q3 appears to achieve nothing but give you an
(unwanted) offset variation with temperature. Changing Q3 to a resistor
avoids any variation with temperature.

Dave

 

[Phil Allison]

"David L. Jones"

I was referring to the more basic (standard) circuit that has no
resistors (or Q3 for that matter), just the two FETs.

** Shame you did not indicate any such thing before.

In this case the two FETs must be matched in order not to get any
DC offset on the output.

** Both are then running with zero GS bias voltage - current level will be
high.

Adding the resistors (or VR3 + Q3) allows the use of non-matched FETs,
but trimming is required for the DC offset.

Adding the transistor Q3 appears to achieve nothing but give you an
(unwanted) offset variation with temperature.

** The Vbe of Q3 ( -2mV per C) likely acts to oppose offset temperature
drift.



...... Phil

 

[David L. Jones]

"David L. Jones"


** Shame you did not indicate any such thing before.

Shame I did. What part of "Q3, RV3 and C35 could be removed" didn't you
understand?
If you remove those components you have nothing left but the two FETs.

** The Vbe of Q3 ( -2mV per C) likely acts to oppose offset temperature
drift.

Perhaps that was the intention, but I recon it might cause more DC
offset variation with temp of its own accord.
The two FETs will after all be reasonably matched in that respect.

Dave