No Connect (NC) pins

[Solidus]

I'm trying to route a BGA1136 package, but about 80-100 of those pins are on the outside fringes and marked NC.

Are No Connect pins not internally connected to the die, or are they just labeled that due to reserved (manufacturer) functions?

That is, can I route through the pads marked No Connect safely without any deleterious effects to the chipset? On .60mm ball diameter and a 1mm pitch ballout I need every inch I can get, and outrouting through the NCs would greatly help the routing process.

 

[(*steve*)]

That's a really good question...

There's certainly a difference between "No Connection" and "Do Not Connect". There's also some cases where pins are labeled as NC*, and * is later noted to mean "do not connect".

In my experience NC pins are literally not connected, however my experience does not include BGA packages in any meaningful way.

Assuming that you can route through these pins, you need to consider the risk of getting a new revision of the chip which may assign a function to that pin.

This document describes the construction of a BGA package. It is worth noting that there are gold bond wires between the chip irself and internal pads connected to the balls.

My gut feeling is that the NC pins are isolated as I'm sure they would not connect additional bond wires for no reason.

The other option is that it is a DSBGA package (but I doubt it as these generally have a much smaller number of "pins". Whilst the balls are directly under the die, there are metal connectors to the die itself (and I have no idea how they make contact). So again, an NC pin would more than likely be floating than connected to *something*.

As a note. My entire BGA experience is trying to use some uSMD-14 devices I purchased by accident.

 

[GonzoEngineer]

An excellent question, because I have often wondered the same thing.

I do know that I got burnt once years ago with a Motorola Microprocessor that had pins marked n.c., but were actually connected to test points for manufacturer testing.

That mistake cost me a lot of money. Si I just always presume n.c. to mean, do not connect!

 

[Solidus]

Fair enough - thanks, both of you, for this advice.

What I may end up doing is deleting the NC balls from the PCB footprint, that way the traces get solder masked over and I'll just have less anchor points for the BGA, but considering I'll still have 800+ pads and centimeters of solder attachment area, likely it won't be an issue.

GonzoEngineer - out of curiousity, were you doing a commercial or homebrew design? I've had quite a few PCBs end up blowing chips due to bad traces from the fab.

Steve - yes, BGAs are a different sort of beast, that's why I tend to prefer the leaded and perimeter-contact varieties of SMD devices, you get more routing freedom and I've never met a QFP, even the larger -208 devices, that can't be done with 8-mil routing. You get a lot of freedom being able to freely run traces under the device. Not with BGAs. It'll be a long time before I work up the courage to try and work with those chip-scale arrays though!

On a side note - what they appear to have done with the chip-scale devices is etch holes in the silicon die and plate them through with metal prior to your typical MEMS buildup. That's starting to become a more and more common manufacturing procedure with normal BGAs and what not because it is easier on the die layout to create a pad at the point of origin than trying to route it through to an exterior mounting pad for bond wires. This is probably even more true in super-high-speed systems.

I know right now I'm experimenting with a couple QFN-24 devices made by Analog Devices to try and build a microprocessor-driven spectrum analyzer. Measuring 4mm by 4mm, even that's pretty damn small for me.

Only problem is, with FPGAs, especially Xilinx in particular, their QFP and QFN selections are very limited, and even those are usually markedly under the BGAs in terms of performance or speed.

So, I suppose they are a necessary evil.

 

[GonzoEngineer]

How many layers are you using for your layout? BGA's get pretty tough without at least six layers and the ability to do blind vias.

(And I gave up fabricating my own boards long ago!)

 

[Solidus]

I'm looking at trying to do it in 4, and that appears to be a push. I'm trying to get the stackup to be something along the lines of VCC, LVDS, GPIO and then GND, with the standard unbalanced signal lines being closest to ground to prevent noise on the other lines. Diff signalling will have its own plane.

My main challenge is the .40mm distance between ball centers - for small-volume PCB fab work, 13mil vias are about the norm, and that don't fly with that ballout pitch.

(and with these BGAs, I see why! haha)

 

[wdancer]

Try to get as much info from the Mfg as you can. Sometimes those pads are also help with thermal transfer and I would suggest still putting down pads just for mechanical strength as well. If the chip heats up enough, it may try to warp the IC if there is nothing holding it down, causing stress on the functional pins. Like GonzoEngineer, I have been burned with ignoring NC pins on BGAs.

 

[Solidus]

Yeah, that is true. The specific device in question here is a Virtex-5 FPGA, which you can see from photos is designed to handle quite the heat dissipation - it has an integrated heat spreader!

So I may decide to lay down some of the NCs, but make gaps in others so that I can place clusters of vias for outrouting.