E
Erik
Hello,
I developed a netlist extractor and a layout vs. schematic (LVS)
application.
It is very early in it's development, but it is functional.
The netlist extractor takes a LEF file with all of its geometries and
converts it into a netlist that consists of transistors and
connections.
The lvs application takes two netlists ( one extracted from a geometry
file, and one from a design schematic) and compares them. If the two
netlists match, you know that your design is properly implemented in
the layout.
I plan on making the extractor and lvs application a more robust and
distributed application using PVM.
Right now it's not fancy, so if your looking for a nice GUI or
something to use in a production environment, you might want to look
somewhere else. And I have only tested it on Linux.
If anyone is interested in the code, you can find it here:
http://www.lechak.info/lvs
If you are interested in the code and have questions or comments please
feel free to contact me via my website.
Thanks,
Erik Lechak
I developed a netlist extractor and a layout vs. schematic (LVS)
application.
It is very early in it's development, but it is functional.
The netlist extractor takes a LEF file with all of its geometries and
converts it into a netlist that consists of transistors and
connections.
The lvs application takes two netlists ( one extracted from a geometry
file, and one from a design schematic) and compares them. If the two
netlists match, you know that your design is properly implemented in
the layout.
I plan on making the extractor and lvs application a more robust and
distributed application using PVM.
Right now it's not fancy, so if your looking for a nice GUI or
something to use in a production environment, you might want to look
somewhere else. And I have only tested it on Linux.
If anyone is interested in the code, you can find it here:
http://www.lechak.info/lvs
If you are interested in the code and have questions or comments please
feel free to contact me via my website.
Thanks,
Erik Lechak
