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Thanks for replying. My electronics knowledge is pretty limited.
Basically, I want to build a system which will close a separate circuit (ie switch on a lamp or motor) every 10th time a button is depressed, and then the process starts again....
This seems a bit obscure, so can't get much off google. The ic 4017 looks like it could do the job, but most examples seem to be for LED chasers and traffic lights, so I can't work out if they can be used to simply close a separate circuit!
Basically, I want to build a system which will close a separate circuit (ie switch on a lamp or motor) every 10th time a button is depressed, and then the process starts again....
This seems a bit obscure, so can't get much off google. The ic 4017 looks like it could do the job, but most examples seem to be for LED chasers and traffic lights, so I can't work out if they can be used to simply close a separate circuit!
hevans1944
Hop - AC8NS
You can always close a separate circuit with a logic-level signal by interposing a switching transistor and a relay. For most applications a 2N7000 MOSFET transistor is easy to hook up: connect logic-level signal to gate, connect a relay coil with a diode across its coil between a positive voltage supply and the drain, connect source to logic common and common of positive voltage supply. You can often use a single 5 V DC power supply for both the logic circuit(s) as well as the relay coil if the relay coil is rated for 3 to 5 V DC operation. Or, if using a higher power supply voltage for the logic, use a relay coil with the appropriate voltage requirement. As @duke37 mentioned, you MUST de-bounce the push-button switch before attempting to use it to "clock" the 4017. A pair of inverters from a 4049 hex inverter package can be wired to do this. Or use the NAND gate circuit below:
Just about any value can be used for R1 and R2 from 1 kΩ to 100 kΩ (if CMOS logic). All the resistors do is pull up the NAND logic gate inputs to logic 1 level when those inputs are NOT shorted to common by the switch S1. The switch "shorts" one of the inputs to common, depending on the position of the switch.
The two gates form an RS (reset-set) flip-flop. With the switch in the position shown, the /Q output is forced to logic 1. This output is applied to one of the upper NAND gate inputs, and combined with the pull-up to logic 1 by R1 on the other input, causes the Q output to go low. This is a stable condition.
As the switch is moved between its two positions, there will be a region where neither R1 nor R2 are connected to ground through the switch and so both of these resistors will pull their logic gate inputs to logic 1 level. This causes no change in the flip-flop output because the top gate already has both inputs at logic 1 level, which causes its output to be at logic 0 level. This logic 0 level applied as an input to the lower NAND gate keeps the /Q output at logic 1 level.
When the switch eventually completes its movement and the top contact of S1 closes, even if just for a moment, the logic 0 level now produced at the top of R1 will cause the Q output to go to logic 1. This is applied to an input on the lower NAND gate, which in conjunction with the logic 1 level applied by R2 to the other gate input, causes /Q to go to logic 0 level. The logic 0 output of /Q is applied to one of the inputs of the upper NAND gate, forcing its output Q to remain high even if the contacts on S1 "bounce" open. And they WILL bounce open, several times before finally remaining closed. That's the reason you need a switch de-bounce circuit.
This is a "classic" switch de-bounce circuit but it does require a single-pole, double-throw switch... a minor inconvenience. In the above diagram, if you connect the two inputs of each NAND gate together it will still work! That means you can replace the NAND gates with a pair of inverters, of which there are six in the 4049 package.
FYI and reference, here is a link to a Wikipedia page listing a lot of 4000 series CMOS logics.
Just about any value can be used for R1 and R2 from 1 kΩ to 100 kΩ (if CMOS logic). All the resistors do is pull up the NAND logic gate inputs to logic 1 level when those inputs are NOT shorted to common by the switch S1. The switch "shorts" one of the inputs to common, depending on the position of the switch.
The two gates form an RS (reset-set) flip-flop. With the switch in the position shown, the /Q output is forced to logic 1. This output is applied to one of the upper NAND gate inputs, and combined with the pull-up to logic 1 by R1 on the other input, causes the Q output to go low. This is a stable condition.
As the switch is moved between its two positions, there will be a region where neither R1 nor R2 are connected to ground through the switch and so both of these resistors will pull their logic gate inputs to logic 1 level. This causes no change in the flip-flop output because the top gate already has both inputs at logic 1 level, which causes its output to be at logic 0 level. This logic 0 level applied as an input to the lower NAND gate keeps the /Q output at logic 1 level.
When the switch eventually completes its movement and the top contact of S1 closes, even if just for a moment, the logic 0 level now produced at the top of R1 will cause the Q output to go to logic 1. This is applied to an input on the lower NAND gate, which in conjunction with the logic 1 level applied by R2 to the other gate input, causes /Q to go to logic 0 level. The logic 0 output of /Q is applied to one of the inputs of the upper NAND gate, forcing its output Q to remain high even if the contacts on S1 "bounce" open. And they WILL bounce open, several times before finally remaining closed. That's the reason you need a switch de-bounce circuit.
This is a "classic" switch de-bounce circuit but it does require a single-pole, double-throw switch... a minor inconvenience. In the above diagram, if you connect the two inputs of each NAND gate together it will still work! That means you can replace the NAND gates with a pair of inverters, of which there are six in the 4049 package.
FYI and reference, here is a link to a Wikipedia page listing a lot of 4000 series CMOS logics.
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