There are a combination of filter effects in both stages.
C3 R4 provide a low pass corner (capacitor in feedback path increases
negative feedback when impedance of capacitor falls below resistor
impedance as frequency rises) at 1/(2*pi*R*C)=1.6 Hz.
C2 R3 provide a second low pass corner by reducing feedback as
impedance of C2 falls below that of R3 as frequency rises, at the same
1.6 Hz.
Then the output of the first stage is coupled to the second stage
through a high pass filter, C4 R5. it rolls off signals below 1.6 Hz.
The feedback of the second stage increases above 1.6 Hz, causing its
gain to roll off at that frequency, for another low pass pole.
The net affect of these 3 low pass poles and one high pass pole is a
band pass filter with a peak response just below 1.6 Hz.
The first stage has a gain of about 51 at the overall peak response
frequency, and the second stage has a gain of another 50 at that
frequency. Total overall gain of 51*50=2550.
The signal is converted to a digital state by two comparators whose
outputs are connected through diodes that only allow the comparators
to pull up. When both comparators output a low voltage, both diodes
are turned off, so the combination would just float if the pull down
resistor were not there to influence the voltage down to ground
(provide a discharge path for the charge stored on the logic chip
input when one of the diodes had previously turned on and charged it
up to almost 5 volts).
By the way, one comparator pulls the output up when the signal goes
positive by more than a diode drop, and one pulls up when the signal
swings negative by more than a diode drop. So any change at about 1.6
Hz from the average level is detected. The diode drop shifts from
average signal are defined by D1 and D2.
If you're interested, here is the data sheet for the timer chip that
cleans up the signal pulses into an "on time":
http://www.fairchildsemi.com/ds/MM/MM74HC4538.pdf
