monte carlo simulation

[microelectronic]

I have designed too many op amps and none of them have any issue with a wide range variations of supply voltage , temperature , corners of process , worst case pvt circumstances , etc . but the problem is the monte carlo analysis by which my op amps are all totally devastated .I know the monte carlo analysis has quite a different scenario from the abovementioned ones and it contains the random mismatches but I tried so many bias circuits with different levels of bias voltages and different schems for sizing the transistors in both 0.35um and 0.18um and mostly for folded-cascode and telescopic topologies and I mostly use the bias circuit presented in gray (p. 847) for folded-cascode , as I already mentioned I used other circuits as well , but mostly that one in the gray . but the results of just monte carlo are terrible(I really do mean it) in either technologies and any bias strategies or any topologies ( either traditional op amps or proposed ones) and any overdrive levels and any sizing regimes (specially large sizes to reduce the random mismatch effects but neither small nor large size did work )and it is really busting and I do not know what the solution to this problem is . I already googled over and over to find a solution to cope with it there was some literature which said to set the overdrive voltages of diff pairs low and the current mirrors high to lower the mismatches and I did so but it did make no difference whatsoever . here is the way by which I perform monte carlo analysis for threshold voltage mismatches(a traditional way which is used mostly in monte carlo analysis) I put a voltage source in series with the gate of all paired transistors but with opposite polarity in each and for example I write the following commands in hspice for an NMOS transistor with w=100um , l=0.18um , m=1.

m1 3 vin+ 1 0 nch l=.18u w=100u m=1
vmcin+ vin+ vinp dvthin+
.param dvthin+ =agauss(0,0.001,1) ( according to the formula (5e-9(v)/sqrt (w*l*m))

is that right? because I have seen way more larger values for that ( for example 0.01 with which my op amps are all completely bled white.)please somebody tells me if the problem stems from the biasing technique or sizing strategy or the way by which I do the simulation or any other cases .

 

[Arouse1973]

Do you have a circuit we can see?
Adam

 

[microelectronic]

As I already mentioned I mostly designed and simulated the conventional folded cascode and improved folded cascode circuits plus the gray's book bias ckts but if by circuit you mean the w/l ratios please let me know.

 

[hevans1944]

Adam, it appears he is designing (and has successfully designed) integrated circuit op-amps and is simulating a new design with HSPICE before committing to silicon. Very old-school, but if you don't already have a design library with recipes, and are doing this from scratch on a new design, it's about the only way to go. Unfortunately, this is (and always will be) above my level of incompetence.

Although we were introduced to monte carlo analysis of discrete circuit designs in college, to ascertain that the circuit would perform within specifications over a range of temperature and component variations, I know nothing about how this applies to integrated circuit design. I suspect the problem is in how the OP is setting up analysis parameters in HSPICE. GIGO principle.

 

[Arouse1973]

Thanks Hop, sorry I thought he was designing a circuit with components.
Adam