R
Robert Strand
Hi,
I though I'd throw this one up for interest, mainly because this is one
isn't modelled properly by spice. I haven't done any measurements to derive
the answer.
As an example consider a simple common source (for the sake fo the argument
N-channel) JFET amplifier where there are no DC paths to the gate only an
AC coupling of a capacitor to the gate.
Now consider the quiescent point. Take the case where the DS voltage isn't
too low, say above 10V. There will be a potential gradient through the
N-channel and the distributed gate will be distributed through this
gradient - this makes the VGS voltage ill- defined. For the purpose of
modelling I considered the distributed JFET as two JFETs in a kind of
cascode connection, except the gates of the two JFETs are joined. Leakage
in the top JFET's DG junction will forward bias the GS diode of the lower
JFET hence the lower JFET will be fully on. Since the P-gate is of low
resistance it will remain at a constant potential of ~0.3V, this pins the
gate of the upper JFET to 0.3V above the source of the lower JFET.
The tricky question is what is the effective channel lengths of the two
JFETs, and would this be a function of the overall DS voltage.
Rob
I though I'd throw this one up for interest, mainly because this is one
isn't modelled properly by spice. I haven't done any measurements to derive
the answer.
As an example consider a simple common source (for the sake fo the argument
N-channel) JFET amplifier where there are no DC paths to the gate only an
AC coupling of a capacitor to the gate.
Now consider the quiescent point. Take the case where the DS voltage isn't
too low, say above 10V. There will be a potential gradient through the
N-channel and the distributed gate will be distributed through this
gradient - this makes the VGS voltage ill- defined. For the purpose of
modelling I considered the distributed JFET as two JFETs in a kind of
cascode connection, except the gates of the two JFETs are joined. Leakage
in the top JFET's DG junction will forward bias the GS diode of the lower
JFET hence the lower JFET will be fully on. Since the P-gate is of low
resistance it will remain at a constant potential of ~0.3V, this pins the
gate of the upper JFET to 0.3V above the source of the lower JFET.
The tricky question is what is the effective channel lengths of the two
JFETs, and would this be a function of the overall DS voltage.
Rob