Measuring the Low state of TTL, CMOS , Pulses

[Davewalker5]

How do you measure the Low states voltage on TTL, CMOS or pulse waveforms?

I have read that the Low states voltage can range from -2 volts vdc to + 2 volts vdc

What would cause the Low state to go to -2 volts vdc? or to +2 volt vdc?

I'm using a Tektonrix TDS 2022
I go to the Horizontal menu button
Then click Window zone , to expand the low states voltage to measure it

 

[(*steve*)]

You place the scope in DC mode.

You note the zero position of the trace, the vertical amplifier setting, and the type of probe.

You calculate the low voltage using the displacement of the low signal from the zero position of the trace.

It would be *very* unusual for any low signal level to be below zero volts.

 

[Davewalker5]

You calculate the low voltage using the displacement of the low signal from the zero position of the trace.

The displacement is in microvolts

The Problem is trying to view the displacement from zero volts and the point of the low states voltage is at

It would be *very* unusual for any low signal level to be below zero volts.

What would cause a TTL or CMOS low state to be at +1 volt or +2 volts?

 

[davenn]

The displacement is in microvolts

? you said it was ± 1 or 2 Volts which is it microvolts or ± 1 or 2 Volts ?

What would cause a TTL or CMOS low state to be at +1 volt or +2 volts?

there may be pull up resistors that affect how low the low state can reach ...

 

[Davewalker5]

you said it was ± 1 or 2 Volts which is it microvolts or ± 1 or 2 Volts ?

In volts

But when "zooming" in on an O-scope of the Low states volts of a TTL or CMOS low state , the displacement from zero volts ground to the low state is in microvolts or millivolts but it can but to +/- 2 volts vdc

The hard part is zooming in on an O-scope without getting all the noise or distortion

 

[(*steve*)]

The displacement is in microvolts

No, the displacement is in divisions (or parts of divisions)

You then multiply the number of divisions by the vertical amplifier setting and then by the probe multiplier to determine the actual voltage.

SO if it is 1/10 of a division, and your vertical scale is 0.5V/division, and you are using a x10 probe, then the voltage is 0.1 * 0.5 * 10 = 0.5V

The Problem is trying to view the displacement from zero volts and the point of the low states voltage is at

Pick a vertical setting which makes this readable.

What would cause a TTL or CMOS low state to be at +1 volt or +2 volts?

TTL or CMOS? The answer is different for each?

For TTL: +2V is a high level, +1V is indeterminate
For CMOS: +2V is indeterminate, +1V is low.



(from http://wiki.openwrt.org/doc/hardware/port.serial)

For valid low level signals at an input, the voltage must be between 0.0 and V_IL

For valid high level signals the voltage must be between V_IH and V_CC

As you can see, these are different for different logic families.

However, your FIRST challenge is to measure it correctly!

 

[Davewalker5]

As you can see, these are different for different logic families.

However, your FIRST challenge is to measure it correctly!

Yes true there is different threshold voltage for each logic families

No, the displacement is in divisions (or parts of divisions)

Yes i know, it's between the ground zero crossing to the first division , its in between

I'm talking about very very small volts, so I have to zoom in

What would cause a TTL or CMOS low state to be at +1 volt or +2 volts?

No , I mean what would cause a Failure to have the TTL or CMOS low state higher then zero volts

What failures would cause the TTL or CMOS low stage to be other then zero volts?

 

[(*steve*)]

Yes true there is different threshold voltage for each logic families

NO! You need to be able to take measurements of the actual voltage correctly.

No , I mean what would cause a Failure to have the TTL or CMOS low state higher then zero volts

It's normal for them not to be exactly zero volts

However:

1. I'm not confident you have measured the voltage correctly yet.
2. We don't know what the output (or input) is connected to, so we can't sensibly comment on whether it's normal or not (it may not be valid, but that doesn't necessarily indicate a fault)

What failures would cause the TTL or CMOS low stage to be other then zero volts?

Almost anything (or perhaps no fault at all).

 

[Davewalker5]

It's normal for them not to be exactly zero volts

Why is that?

I'm not confident you have measured the voltage correctly yet.

I'm "zooming in" or using "window zoom" on my O-scope

But it's magnifying noises

How do you measuring the low state compared to the zero crossing point on the O-scope? how do u set it up

Should i use a Digital volt meter instead to measure the low state of an TTL or CMOS low state voltage? instead of an O-scope

What failures would cause the TTL or CMOS low stage to be other then zero volts?
Almost anything (or perhaps no fault at all).

But what are some common or general failure of cause the TTL or CMOS low state to be other then zero volts? that is not normal

 

[(*steve*)]

Why is that?

Did you see the image I posted? There are a range of output voltages. which depend on a whole lot of things that you refuse to tell us.

But it's magnifying noises

Of course it is. Can't you estimate?

I'm "zooming in" or using "window zoom" on my O-scope

Fine, you use a method different to what I suggest and ask me what is happening. I have no idea what these functions do, so I can't tell you how you can measure a voltage.

Have you tried (ever?) doing things the way you're asked to do them?

But what are some common or general failure of cause the TTL or CMOS low state to be other then zero volts? that is not normal

No, it's perfectly normal for them to be other than zero volts.

In order to suggest a failure we must first know:

1. What the actual output voltage is
2. What the logic family is
   
3. What the circuit is
4. What the expected range of voltages is given the circuit

Only then can we decide IF there's is a fault, and IF there is a fault we might be able to offer some conjecture as to the reason.

So far we've not even gotten past step 1 of that process.

 

[Davewalker5]

No, it's perfectly normal for them to be other than zero volts.

Why would it be normal? i don't get it

You're saying that all TTL and CMOS logic chips don't output a low state at zero volts, why is that? any reason why they do that?

How do you measure the low state of a TTL or CMOS chip? what is your ways of doing this

The way i'm doing it is wrong

 

[(*steve*)]

Let's just do one thing at a time.

Why would it be normal? i don't get it

You're saying that all TTL and CMOS logic chips don't output a low state at zero volts, why is that? any reason why they do that?

The output voltage of a TTL logic device must be 0.2V or lower to be valid. There is a transistor pulling to output low. The transistor cannot pull the output all the way down to 0V (although it can get close if there is no load)

With the specified maximum load, the output voltage can rise as high as 0.2V and still be in spec.

If you place a larger load on the output it will rise higher, possibly higher than the 0.2V specified as the maximum output low voltage, possibly higher even that the maximum input low voltage (0.8V). But, depending on the circuit, this might be normal and expected.

How do you measure the low state of a TTL or CMOS chip? what is your ways of doing this

1. Set up your scope with the x10 probe connected to ground and DC coupled. Adjust the trace position so it is aligned with the lowest graticule on your scope.
2. Set the vertical amplifier to 100mV per division.
3. Probe the supply voltage to your logic. If it is 5V, the trace should rise 5 divisions up the screen
4. Probe the low logic level.
5. Estimate how far the signal is above the lowest graticule. Is it 1/2 a division, is it 1/5 of a division (often there are some smaller divisions on the display to help you with this).
6. Calculate the input voltage. (if 3 was true, then you have 1volt per division, so 1/5 of a division means 0.2V)

If the difference between the ground level and the low logic level is to small to calculate then you can either assume it's very close to ground, or you can repeat the steps above with a more sensitive vertical amplifier setting. If you do this, step 3 might cause the trace to vanish off the top of the display. That's OK, it won't damage anything.

It would help if you can take a picture of the screen of the oscilloscope at steps 1, 5, and 4, and also a picture of the controls of the scope (which should not change from before you took the first picture). That way we can check your work.

If you end up using 20mV/Div, a x10 probe, and you see 1/3 of a division difference between ground and the low level logic signal then the low level voltage is approx 10 * 1/3 * 20mV, or about 67mV.

Now, I'm assuming you know

• how to set the vertical scale on the scope,
  
• if you have a x10 probe (or something different)
• how to set the horizontal timebase to something sensible
• how to adjust the trace position
• How to connect the probe to the circuit (there will be 2 connections)
  
• What a division on the screen is (and what the graticule is)

If you have ANY doubts about ANY of these, then ASK. If you don't ask, I will assume that knowledge.

 

[Davewalker5]

If you place a larger load on the output it will rise higher, possibly higher than the 0.2V specified as the maximum output low voltage

Why does the output rise when you put a load on it? that doesn't make sense

Now, I'm assuming you know

• how to set the vertical scale on the scope,
• if you have a x10 probe (or something different)
• how to set the horizontal timebase to something sensible
• how to adjust the trace position
• How to connect the probe to the circuit (there will be 2 connections)
• What a division on the screen is (and what the graticule is)

Yes i know this

Probe the low logic level.

I can't, because it's toggling or alternating from high and low state

It's a Pulse train, I'm trying to measuring the voltage of the low state of a logic pulse train

Logic TTL pulse train or a CMOS Logic Pulse Train

If the difference between the ground level and the low logic level is to small to calculate then you can either assume it's very close to ground,

Yes it is very close to ground, which is the problem

The O-scope set on a sensitive vertical amplifier setting just will pickup noise and will distort the low state signal , it will be a slope or ramp with noise on the O-scope

That's why I was using the Zoom function and Window Zone function on my O-scope to magnify the logic low state signal because it's so close to ground

I'm trying to measure logic low state signals very very close to ground

Plus the Logic TTL and CMOS are pulse trains, so I can't use a DVM meter to measure the DC millivolts or micro volts of the logic low state because it's a pulse train , so the DVM meter is toggling and alternating

I was thinking of putting a Diode in series on the RED probe of my DVM meter so i can measure only the logic low state of a pulse train TTL or CMOS signal to measure the microvolts of a logic low state that is very close to ground

 

[(*steve*)]

Why does the output rise when you put a load on it? that doesn't make sense

Because the voltage will change when you place a load on something that does not have a zero impedance.

In this case the load is always assumed to be toward the other rail, so it might be a resistor between Vcc and the output.

The fact you say it makes no sense means that you are trying to run before you can crawl.

I can't, because it's toggling or alternating from high and low state

It's a Pulse train, I'm trying to measuring the voltage of the low state of a logic pulse train

Logic TTL pulse train or a CMOS Logic Pulse Train

Then probe that! (sheesh!)

Yes it is very close to ground, which is the problem

That's the problem?!?!?! (read in an exasperated John Cleese voice)

That's what you WANT.

The O-scope set on a sensitive vertical amplifier setting just will pickup noise and will distort the low state signal , it will be a slope or ramp with noise on the O-scope

Firstly, it's an oscilloscope, a scope, or a cro, or even just "it".

Secondly, if you have connected it correctly (refer to my question about you knowing how to probe the circuit) then you should not have significant noise unless you wind the vertical sensitivity right up, and even then you should only have a very small amount. Also you are FAILING to tell me what actual settings you're using and the change in the level on the display.

Thirdly, you have provided no pictures.

I will now patiently wait for pictures.

 

[Davewalker5]

Because the voltage will change when you place a load on something that does not have a zero impedance.

The output pin of op-amps and logic gates should be low impedance

I will upload the pictures tomorrow , I don't have my camera adapter right now but i do have the pictures taken

you will see the noise and the slope/ramp it makes when you adjust the voltage per division on the O-scope when trying to measure the low logic state that is very very close to ground

 

[Davewalker5]

Here is the pictures

Picture Pic#1 is what the low state looks like
Picture Pic#2 is when i increase the voltage per division more
Picture Pic#3 I increase the volts per division more
Picture Pic#4 I increase the volts per division more

It adds more and more noise , plus it slants,slopes, ramps the low state

Any reason why?

 

[(*steve*)]

Picture Pic#1 is what the low state looks like

And if you look very closely you can see a slight slant on the low logic level.

Picture Pic#2 is when i increase the voltage per division more

No, you're decreasing the volts per division. And that slight slope becomes more noticeable.

Picture Pic#3 I increase the volts per division more

(decrease V/div -- or increase the sensitivity)

Picture Pic#4 I increase the volts per division more

No, in this example you actually turned on averaging. This acts to remove random noise, which it has.

What you have failed to do is show me where zero is. If you followed my instructions it should be right at the bottom of the display. Did you follow my instructions?

I also don't know if the 500mV/Div takes into account the probe or not. Do you know? Do you know what you are measuring. You suggested it was logic, but in a recent post you mentioned op-amps.

You also STILL haven't indicated what you're actually measuring. Is it Logic? Is it an input or an output? Is it TTL, CMOS, or something else? What is the device? Do you have a schematic?

Please don't make this such a painful process. If you *MUST* make it painful, at least offer me my going hourly rate to put up with it.

Oh, and I don't see anything intrinsically wrong with the signal, however that is based on a heap of assumptions that I wouldn't have to have made if you had followed my instructions.

 

[Davewalker5]

And if you look very closely you can see a slight slant on the low logic level.

True , I agree

No, you're decreasing the volts per division. And that slight slope becomes more noticeable.

Yes true

But don't u think it's the O-scope resolution problem, that is why the slope becomes more noticeable

Because I think it's a Resolution problem of the O-scope

(decrease V/div -- or increase the sensitivity)

Yes when you increase the sensitivity the O-scope resolution becomes a problem right?

No, in this example you actually turned on averaging. This acts to remove random noise, which it has.

Yes i know, that's why i turned on averaging to show you it's not the noise, its the O-scopes resolution that's becoming a problem.

You also STILL haven't indicated what you're actually measuring. Is it Logic? Is it an input or an output? Is it TTL, CMOS, or something else? What is the device? Do you have a schematic?

I really don't know what i'm measuring

I think it's op amps that are creating the pulse train, but I don't know what kind of circuit this would be called that does this

They use to use Op amps to create pulse trains before TTL and CMOS , but I'm not sure that is the name of these types of circuits

Plus I just want to know how to measure the low state voltage of a TTL or CMOS in general , doesn't have to be applied to a circuit , just in general knowledge

 

[(*steve*)]

Yes when you increase the sensitivity the O-scope resolution becomes a problem right?

You seem to fail to understand that as you magnify things they appear to get bigger.

Yes i know, that's why i turned on averaging to show you it's not the noise, its the O-scopes resolution that's becoming a problem.

It's NOT the oscilloscope's resolution. You're seeing noise. That noise is probably really there.

They use to use Op amps to create pulse trains before TTL and CMOS , but I'm not sure that is the name of these types of circuits

Do you have a schematic? Can't you tell me what the @#$%ing circuit actually is?

Plus I just want to know how to measure the low state voltage of a TTL or CMOS in general , doesn't have to be applied to a circuit , just in general knowledge

Since you don't even know what you're measuring, how are you even going to apply this?

You are really trying to make this hard for me aren't you?