Greetings,
You might have seen me posting a few things about Z80s, ROM Programmers, switch debouncing etc. Well it has all been with a view to this. Here is the more or less nearly finalised design for the programmer end. A Z80 and some memory will be added to this in the next stage. I'm sure this is far from perfect so any comments / criticisms would be much appreciated.
I've left out the bypass capacitors in the diagram for simplicity.
Is that a daft place to put the protection diode for the power supply?
The reset switch sends a pulse of about half a second. It is also triggered at power on by the 220nF capacitor across the switch. The transistor provides an inverse pulse for ICs with active low lines.
The timing capacitors / resistors in the audio interface also limit the data speed and could probably go quite a bit lower (i'll experiment with that later)
The programmer itself had a few challenges and I've no idea if this solution is going to work. When the byte counter reaches 8 it resets the counter and sends a write signal. This is inverted for the address counter so that it doesnt increment till after the write. I put that 100nF capacitor to ground on the write line to act as a slight delay to ensure that the address and data busses are read correctly.
You might have seen me posting a few things about Z80s, ROM Programmers, switch debouncing etc. Well it has all been with a view to this. Here is the more or less nearly finalised design for the programmer end. A Z80 and some memory will be added to this in the next stage. I'm sure this is far from perfect so any comments / criticisms would be much appreciated.
I've left out the bypass capacitors in the diagram for simplicity.
Is that a daft place to put the protection diode for the power supply?
The reset switch sends a pulse of about half a second. It is also triggered at power on by the 220nF capacitor across the switch. The transistor provides an inverse pulse for ICs with active low lines.
The timing capacitors / resistors in the audio interface also limit the data speed and could probably go quite a bit lower (i'll experiment with that later)
The programmer itself had a few challenges and I've no idea if this solution is going to work. When the byte counter reaches 8 it resets the counter and sends a write signal. This is inverted for the address counter so that it doesnt increment till after the write. I put that 100nF capacitor to ground on the write line to act as a slight delay to ensure that the address and data busses are read correctly.
