[LTSpice] Why is 1n4148 so slow?

[Chris Carlen]

Greetings:

A 1n4148 should have a Trr of about 4ns, but the sim gives about 15ns!

Why is that?



Version 4
SHEET 1 880 680
WIRE -16 240 -16 160
WIRE -16 352 -16 320
WIRE 112 160 -16 160
WIRE 224 160 176 160
WIRE 224 208 224 160
WIRE 224 336 224 288
FLAG 224 336 0
FLAG -16 352 0
SYMBOL diode 112 176 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 208 192 R0
SYMATTR InstName R1
SYMATTR Value 250
SYMBOL voltage -16 224 R0
WINDOW 3 -151 173 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(-50 50 0 1n 1n 500n 1u)
SYMATTR InstName V1
TEXT -168 506 Left 0 !.tran 0 3u 0 1n



Thanks for input.


--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

 

[Jim Thompson]

Greetings:

A 1n4148 should have a Trr of about 4ns, but the sim gives about 15ns!

Why is that?
[snip]

Thanks for input.

Are you simulating it in a way that matches the test method on the
data sheet?

...Jim Thompson

 

[Genome]

Greetings:

A 1n4148 should have a Trr of about 4ns, but the sim gives about 15ns!

Why is that?
Thanks for input.

Indeedy, what Jim says. Change your resistor to 100R and make your pulse 1.6
and -6V.

DNA

 

[legg]

Indeedy, what Jim says. Change your resistor to 100R and make your pulse 1.6
and -6V.

Note that dI/dT in the JEDEC test set-up is determined by the
generator's fall time - "<1nS" effectively producing 76A/uSec in this
case.

This is roughly the same effect as a perfectly fast source operating
in series with 100nH - a fairly high 'stray' inductance value, but one
not totally impossible to introduce accidentally in a sloppy physical
test set-up.

dI/dT affects the peak reverse current, rate of total charge removal
and trr, with no other test characteristics being altered.

RL

 

[Chris Carlen]

Greetings:

A 1n4148 should have a Trr of about 4ns, but the sim gives about 15ns!

Why is that?
[snip]
Thanks for input.

Are you simulating it in a way that matches the test method on the
data sheet?

...Jim Thompson

Good point, lemme see...



Oh, I get it.



Thanks for the input.



Good day!



--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

 

[Chris Carlen]

Note that dI/dT in the JEDEC test set-up is determined by the
generator's fall time - "<1nS" effectively producing 76A/uSec in this
case.

This is roughly the same effect as a perfectly fast source operating
in series with 100nH - a fairly high 'stray' inductance value, but one
not totally impossible to introduce accidentally in a sloppy physical
test set-up.

dI/dT affects the peak reverse current, rate of total charge removal
and trr, with no other test characteristics being altered.

You mean of course that it can reduce the peak Irr, by blurring it out
over a ringy-thingy, right?

I tried simulating as you are saying, by making my generator *really*
fast with 10ps rise/fall, and introducing 100nH.

That gives just about the same peak Irr and Trr for the first half cycle
of the ring.

Actually, it looks like a stray inductance I wouldn't feel too shabby about!

Well, that's if I did it on a breadboard like I do most things in a
curious hurry.

But if done on a PCB, it could be much better.


Thanks for the input.

Good day!




--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.