Low noise signal clamping

[Dirk Bruere at NeoPax]

I need to clamp the input of a 24 bit ADC to prevent any transients from damaging it. I suspect diodes are going to be too noisy, and am looking at using discrete transistors with their bases tied to the rails though a low value resistor. Is this viable? Does anyone have any suggestions?

 

[Spehro Pefhany]

I need to clamp the input of a 24 bit ADC to prevent any transients from damaging it. I suspect diodes are going to be too noisy, and am looking at using discrete transistors with their bases tied to the rails though a low value resistor. Is this viable? Does anyone have any suggestions?

That's the best I've been able to come up with (you don't need to tie
the bases to the rails- a different voltage might be preferable). If
you can't tolerate enough series resistance to make this sufficient,
consider the series depletion FETs that JL discussed here some time
ago.



Best regards,
Spehro Pefhany

 

[Dirk Bruere at NeoPax]

That's the best I've been able to come up with (you don't need to tie

the bases to the rails- a different voltage might be preferable). If

you can't tolerate enough series resistance to make this sufficient,

consider the series depletion FETs that JL discussed here some time

ago.

Thanks.
I'm a long time out of designing with discrete transistors - have you any suggestions for a low noise part in SOT23 package?

Dirk

 

[Joerg]

I need to clamp the input of a 24 bit ADC to prevent any transients
from damaging it. I suspect diodes are going to be too noisy, and am
looking at using discrete transistors with their bases tied to the
rails though a low value resistor. Is this viable? Does anyone have
any suggestions?

Why should diodes be noisy here? While the ADC input is within operating
range they aren't conducting.

I am assuming you want to protect the ADC input against the ESD spike
from hell or something like that. This is how it's done:

a. Resistor from input signal to diodes. 1k or so, depends on how much
you can tolerate. More is better but make that a longer body resistor to
reduce the chance that a spark jumps across. That limits the spike
current in general.

b. Diodes to the positive and negative rail of the ADC. You can use
SOT23 duals (series) or even SC75 if space is tight.

c. Resistor 200 ohms from there to the ADC input.

This results in the lion's share of the ESD pulse going through the
external diodes instead of the parasitic substrate diodes in the ADC.
Even if the "pulse from hell" drives the diode 2V beyond a rail the
current going through the ADC substrate would remian under 10mA.

Of course, you can also generate helper voltages lower than the rails
and leave out that 200 ohms resistor but that is more effort.

 

[miso]

Why should diodes be noisy here? While the ADC input is within operating
range they aren't conducting.

I am assuming you want to protect the ADC input against the ESD spike
from hell or something like that. This is how it's done:

a. Resistor from input signal to diodes. 1k or so, depends on how much
you can tolerate. More is better but make that a longer body resistor to
reduce the chance that a spark jumps across. That limits the spike
current in general.

b. Diodes to the positive and negative rail of the ADC. You can use
SOT23 duals (series) or even SC75 if space is tight.

c. Resistor 200 ohms from there to the ADC input.

This results in the lion's share of the ESD pulse going through the
external diodes instead of the parasitic substrate diodes in the ADC.
Even if the "pulse from hell" drives the diode 2V beyond a rail the
current going through the ADC substrate would remian under 10mA.

Of course, you can also generate helper voltages lower than the rails
and leave out that 200 ohms resistor but that is more effort.

By low noise, I presume they can't tolerate a lot of series resistance.

If you look at ESD testing, there is human body model and machine model.
Machine model is for assembly, and human body model is real life. (Of
course plugging a sensor into an instrument can look a lot more like a
machine model than a human model.) If you look at the human body model
circuit, just adding capacitance can greatly reduce the ESD spike.

It isn't clear to me why a transistor will be any quieter than a
discrete diode, other than there is less capacitive coupling. But if
this low noise circuitry, I have to presume the impedances involved are
small as well, so the cap can't couple in that much noise, given a
voltage divider with the cap at omega*C.

The chips generally have nfet ESD protection, i.e. body diode in the
negative direction and snap back in the positive direction. Maybe a
small nfet with low breakdown voltage on the input will do the trick.
But this isn't all that different from using a transorb diode.

Inducing latchup is another story. Seems to me series resistance and
diodes to the rails is the only solution. But I never saw the depletion
mode fet circuit. If that circuit goes high-Z in both directions, that
would reduce latchup.

 

[Joerg]

By low noise, I presume they can't tolerate a lot of series resistance.

Yeah, that's why I mentioned a 1k. Normally I'd go higher. If this is a
concern Dirk could look at inductors instead. A 24-bit ADC will most
likely opeate <100kHz.

If you look at ESD testing, there is human body model and machine model.
Machine model is for assembly, and human body model is real life. (Of
course plugging a sensor into an instrument can look a lot more like a
machine model than a human model.) If you look at the human body model
circuit, just adding capacitance can greatly reduce the ESD spike.

If the transients are human-body model it can be ok. Sometimes they
aren't. For example, a client of mine had outdoor electronics die during
thunderstorms, that's a whole 'nother ballgame.

It isn't clear to me why a transistor will be any quieter than a
discrete diode, other than there is less capacitive coupling. But if
this low noise circuitry, I have to presume the impedances involved are
small as well, so the cap can't couple in that much noise, given a
voltage divider with the cap at omega*C.

The chips generally have nfet ESD protection, i.e. body diode in the
negative direction and snap back in the positive direction. Maybe a
small nfet with low breakdown voltage on the input will do the trick.
But this isn't all that different from using a transorb diode.

Transzorbs have huge tolenrances so one would have to looks at abs max
and meybe discuss if with the ic designers are the mfg. If one is
granted access to them, that is. That might require lots of cajoling and
kowtowing.

Inducing latchup is another story. Seems to me series resistance and
diodes to the rails is the only solution. But I never saw the depletion
mode fet circuit. If that circuit goes high-Z in both directions, that
would reduce latchup.

That almost requires a comparator but can be done. I'd do it with
enhancement mode FETs though, to make sure that it is off even when
unpowered.

 

[Maynard A. Philbrook Jr.]

By low noise, I presume they can't tolerate a lot of series resistance.

If you look at ESD testing, there is human body model and machine model.
Machine model is for assembly, and human body model is real life. (Of
course plugging a sensor into an instrument can look a lot more like a
machine model than a human model.) If you look at the human body model
circuit, just adding capacitance can greatly reduce the ESD spike.

It isn't clear to me why a transistor will be any quieter than a
discrete diode, other than there is less capacitive coupling. But if
this low noise circuitry, I have to presume the impedances involved are
small as well, so the cap can't couple in that much noise, given a
voltage divider with the cap at omega*C.

The chips generally have nfet ESD protection, i.e. body diode in the

http://arxiv.org/pdf/1205.4604.pdf

That may interest you.

Jamie

 

[Spehro Pefhany]

Thanks.
I'm a long time out of designing with discrete transistors - have you any suggestions for a low noise part in SOT23 package?

Dirk

I've just used general purpose parts like MMBT4401/3. If your clamping
is inside a loop with a current-limited op-amp or diff-amp output, a
little leakage won't matter.

This whole clamping thing is irritating. To do things right requires a
whole bunch of inelegant stuff. To not do things right invites weird
behavior or even failures. If the ADC makers don't or can't put it
on-chip, there ought to be a circuit block like a digital voltage
translator that lets you go from a +/-7V op-amp to a +/-5V ADC without
worry or undue effect on the signals.

 

[stratus46]

I need to clamp the input of a 24 bit ADC to prevent any transients from damaging it. I suspect diodes are going to be too noisy, and am looking at using discrete transistors with their bases tied to the rails though a low value resistor. Is this viable? Does anyone have any suggestions?

Would something like this help?

http://www.analog.com/static/imported-files/data_sheets/AD8036_8037.pdf

G²

 

[Tim Williams]

http://arxiv.org/pdf/1205.4604.pdf

That may interest you.

Heh, Fig.2 shorts +V to -V.

Yay, LaTeX formatting and equations. ;-) Although the paragraph and margin
settings aren't so great.. oh well, he's only an astronomer. Wonder if the
schematics were also LaTeX (there's a package for that) or what. Seem to be
vector.

Tim

 

[Maynard A. Philbrook Jr.]

Heh, Fig.2 shorts +V to -V.

Yes I notice that, but most people that know better would
short that.
I did put that bridge in the sim and it seems to work well.

One problem with this of course is the Vbe break down. You must not
exceed that..

Yay, LaTeX formatting and equations. ;-) Although the paragraph and margin
settings aren't so great.. oh well, he's only an astronomer. Wonder if the
schematics were also LaTeX (there's a package for that) or what. Seem to be
vector.

Tim

Years ago I made a double balance ring modulator using a config that
looks a lot like this transistor bridge!

Jamie

 

[Dirk Bruere at NeoPax]

Thanks for the replies.
The problem is a +/- 2V5 ADC being driven from a +/- 15V opamp. The latter is a 4:1 voltage divider but I could still get +/- 4V approx under some weird unspecified conditions. AFAIK this doesn't happen in practice, but it might be possible under extreme operating conditions resulting from a failurein another part of the system.

 

[Dirk Bruere at NeoPax]

Thanks for the replies.

The problem is a +/- 2V5 ADC being driven from a +/- 15V opamp. The latter is a 4:1 voltage divider but I could still get +/- 4V approx under some weird unspecified conditions. AFAIK this doesn't happen in practice, but it might be possible under extreme operating conditions resulting from a failure in another part of the system.

Here is what I have decided to do. Feed the signal via a 10K resistor from the 15V op amp divider to a 2V5 op amp in a resistorless voltage follower mode and then onto the ADC. The idea being that any overvoltage will be clamped by the inputs of the 2V5 opamp follower. Using something like a LTC1150the additional noise and drift should be negligible.

Dirk

 

[Spehro Pefhany]

Here is what I have decided to do. Feed the signal via a 10K resistor from the 15V op amp divider to a 2V5 op amp in a resistorless voltage follower mode and then onto the ADC. The idea being that any overvoltage will be clamped by the inputs of the 2V5 opamp follower. Using something like a LTC1150 the additional noise and drift should be negligible.

Dirk

The LTC1050 noise performance is specified with a 100R source
resistance, and even so it won't allow better than 18 bit performance
with a 5V ADC span, even with a 10Hz BW.

I wonder what happens to the noise with a relatively high source
resistance.. that type of amplifier typically has little charge
packets coming out of the inputs at the sampling frequency.

An ideal 10K resistor has a Johnson noise of >4uV RMS at 50°C & 100kHz
BW (reasonable, assuming something like a higher end audio ADC is
being used). Call it ~25uV p-p. Not so much of an issue if the
application is low BW.


Best regards,
Spehro Pefhany

 

[Dirk Bruere at NeoPax]

The LTC1050 noise performance is specified with a 100R source

resistance, and even so it won't allow better than 18 bit performance

with a 5V ADC span, even with a 10Hz BW.



I wonder what happens to the noise with a relatively high source

resistance.. that type of amplifier typically has little charge

packets coming out of the inputs at the sampling frequency.



An ideal 10K resistor has a Johnson noise of >4uV RMS at 50�C & 100kHz

BW (reasonable, assuming something like a higher end audio ADC is

being used). Call it ~25uV p-p. Not so much of an issue if the

application is low BW.

The ADC is a CS5532 24 bit low speed conversion chip. We read it around 6HzIIRC and effectively oversample the crap out of the signal with hundreds of readings per data point. For all intents and purposes, the bandwidth of interest is <20Hz

Dirk

 

[Maynard A. Philbrook Jr.]

Then rail diodes is all you need,

jamie

 

[Tim Williams]

Yes I notice that, but most people that know better would
short that.
I did put that bridge in the sim and it seems to work well.

One problem with this of course is the Vbe break down. You must not
exceed that..

If you're lucky enough to find invertible transistors, that isn't a problem.

I don't know if anyone makes high Veb transistors anymore, but I have
noticed those low-saturation transistors (ZTX651, PBSS303x, etc.) have high
inverted hFE at least (~hundreds).

Tim

 

[miso]

ADG465 and/or JFETs used as diodes?

Vladimir Vassilevsky
DSP and Mixed Signal Designs
www.abvolt.com

Take a look at the top circuit on this page.
http://www.recursion.jp/prose/bicrrnt/index.html
You can omit the resistor.

For small voltages, the jfet sits in triode. For a large voltage swing,
the jfet with a positive vds goes into current limiting, i.e. reaches
IDSS. The other device gets turned on even stronger, not that it matters
due to the current limiting of the other jfet.

The idss has to be low enough not to trigger latch-up. I doubt any chip
manufacturer would go lower than say 40ma. The deal here though is the
higher the IDSS, the stronger the jfet, which in turn means lower
resistance when in triode. So you pick the jfet IDSS to be just under,
or even around 40ma. Most chips can do 100ma. Or to be exact, most
people quit testing latch-up at 100ma injection. Ever since epi cmos
became the standard in processing, you don't hear all that much about
latch-up.

Most jfets are symmetrical physically, so the source and drain are
interchangeable. That is, the true source and drain are determined by
applied voltages rather than what it says on the pins.

 

[whit3rd]

I need to clamp the input of a 24 bit ADC to prevent any transients from damaging it. I suspect diodes are going to be too noisy, and am looking at using discrete transistors with their bases tied to the rails though a low value resistor. Is this viable? Does anyone have any suggestions?

I'd use an inverting op amp, powered on the same rails as your ADC,
and diode-clamp at the pseudo-ground input of the op amp. It takes
more parts, but you can use big diodes (the stray capacitance doesn't charge).

It inverts your signal, of course.

A big Zener to ground works better than a diode to Vcc, which can blow the power
supply's other client chips.

 

[George Herold]

I need to clamp the input of a 24 bit ADC to prevent any transients from damaging it. I suspect diodes are going to be too noisy, and am looking at using discrete transistors with their bases tied to the rails though a low value resistor. Is this viable? Does anyone have any suggestions?

Are you worried about the leakage current of the reverse biased diode,
or the noise of the series resistor.

If it's the diode current then you can use part of a small transistor instead of a diode. (less leakage.) I think it's the c-b junction. I've got anice B.Pease paper at work that has typical numbers.

George H.