JK flip flop with pulse output

[mnbv0987]

Is there a name for a circuit that is a JK flip-flop except the outputs are held high only for a single clock cycle (resetting to low on the following clock) rather than being held high indefinitely?

Thanks!
M

 

[(*steve*)]

I guess you want the state to initially change with the clock rising edge and to be reset on the clock falling edge?

If you have a clocked JK flip flop which changes state on the positive edge of the clock and has a clear input which is active on the falling edge, then simply connect the clock input and the clear input together.

If the clock and clear work on other edges, then you may need an inverter or two to get the edges going the right way.

 

[mnbv0987]

Yeah, that's what I'm going for. Thanks, that's a good idea! Does this type of circuit have a specific name that I could use to describe it to somebody?

M

 

[(*steve*)]

Not as far as I'm aware.

You want to look for an edge triggered JK flip flop with a synchronous clear, unfortunately clear and preset are asynchronous.

The easiest way is to use some logic between the clock and either Q or Q-bar to derive a clear signal.

If the flip flop is positive edge triggered, you want a falling edge on the clock, combined with a low on q-bar to generate the appropriate level on the clear input. This is either a NOR or OR function

If the flip flop is positive edge triggered, you want a falling edge on the clock, combined with a low on Q-bar to generate the appropriate level on the clear input. This is either a NOR or OR function

If the flip flop is negative edge triggered, you want a rising edge on the clock, combined with a high on Q to generate the appropriate level on the clear input. This is either a NAND or AND function

It has no specific name that I'm aware of. I will call it "Bruce"

 

[mnbv0987]

Awesome, thanks! And Bruce it is! =)