IR2110 Functional Block Diagram

[BlackMelon]

Hello,

The block diagram is on the IC's datasheet. Let Vdd = 5V, and Vss = 0V. After the IC has been disabled (SD=high), I fed a square wave (5V/0V) to HIN pin. When the square wave is low, will this cause an ambiguous Q of the upper SR-flip flop? If so, will it ruin the operation of the IC?

About the pulse gen block, why do we have to have it? Will its upper and lower outputs be in-phase with the output of the upper NOR gate?

Thank You
BlackMelon

 

[kellys_eye]

Block diagram? Nothing shown.....

 

[Minder]

Once you set SD =1 then any input on LIN or HIN all output from these inputs are disabled.
M

 

[dorke]

SD,stands for Shut Down.
Looking at Figure. 1 in the data sheet revels that for SD=0 or 1 the output is well defined.
Why do you think SD=1 will cause any problems?

 

[BlackMelon]

Once you set SD =1 then any input on LIN or HIN all output from these inputs are disabled.
M

Why do you think SD=1 will cause any problems?

Please see my attachment "Block1". The block diagram is extracted from "https://www.infineon.com/dgdl/ir2110.pdf?fileId=5546d462533600a4015355c80333167e".


The driver operation is explained more in AN-978, saying about the MOSFET driver family of IR.
Here is AN-978: "https://www.infineon.com/dgdl/an-978.pdf?fileId=5546d462533600a40153559f7cf21200".
At the end of the third paragraph of page 5, I don't understand why the writer has to mention the rising/falling edges. I think the SR-flip flop works as in my attachment "Block2". Why do we have to care about the edges?

Thank You

 

[dorke]

Well,
The block diagram is merely a conceptual thing.
You shouldn't take it to be complete or accurate.
Look at the AN-978,you can find a "different block diagram" at fig.2 page 3 !

You are thinking of the S-R -Q block to be implemented like the "school dual crossed gates" and thus are thinking about the S=R=1 as forbidden input combination (outputs at both logical fault and race condition after that input combo).

It isn't the case here like figure one of the datasheet shows clearly.
Not only that,if there was a potential problem than the manufacture would state it loudly....
And lastly, that situation can be solved simply in a specific implementation.

 

[BlackMelon]

Thank you everyone. In fact, I saw the figure 1 many times. Most designers present it on their websites. I shouldn't have taken the block diagram too seriously and should have just believed what most people do online.

 

[BlackMelon]

In AN-978, page5, paragraph 3, I have a doubt about the following words:
"As shown in Figure 2 the on/off commands are transmitted in the form of narrow pulses at the rising and falling edges of the input command. They are latched by a set/reset flip-flop referenced to the floating potential."

Suppose that I input a signal to HIN like in the attachment,
Will the narrow pulses be like this?
Will it come out of the pulse generator?
Will it make the latch "A" have the QA-bar output like what I have sketched?

 

[dorke]

In AN-978, page5, paragraph 3, I have a doubt about the following words:
"As shown in Figure 2 the on/off commands are transmitted in the form of narrow pulses at the rising and falling edges of the input command. They are latched by a set/reset flip-flop referenced to the floating potential."

Suppose that I input a signal to HIN like in the attachment,
Will the narrow pulses be like this?
Will it come out of the pulse generator?
Will it make the latch "A" have the QA-bar output like what I have sketched?

AN-978 explanation of how the IC works relates to a different "block diagram" than the one in the datasheet.
You can find it on page 3,figure 2.
So let's refer to it(below).

About your questions:
1.Will the narrow pulses be like this?
No way to know, since there are no details about how the Pulse-Discriminator is build.

2.Will it come out of the pulse generator?
Yes

3.Will it make the latch "A" have the QA-bar output like what I have sketched?
Not very important.
If you look at the 2 different "block diagrams" ,
you can see the the driving Mosfets are shown in one as P-channel and in the other as N-channel !
So what is it?may be even CMOS? we obviously don't know.
The structure is shown as a totem-pole ,
in which to get a "1" on the output the upper mos should be on and the lower should be off.
Vise versa for the output at "0".
From that you can conclude (if you knew the structure) what are the levels needed from the "Final Latch Logic"

4.Why do we have to care about the edges?
The app. note talks about reduces power consumption with edges.

Hope that helps.

 

[dorke]

There are some other App. Notes that can help:
AN-1092
DT92-2A

 

[BlackMelon]

Thank you Dorke. I'll be reading them. If I have any further questions, I will let everybody know here.