How to convert VHDL / Verilog code to layout?

[boki]

Hi, All:

Could you please tell me or give me some hint to convert VHDL /
Verilog code to layout?.

Thanks a lot!

Boki.

 

[Russ]

In a nutshell:
o Run synthesis
o floorplanning
o timing analysis
o library create
o formal verification
o place & route / Clock
o signal integrity
o Design for Test
o Extraction
o DRC/LVS
o Tape-out (priceless!!!!)

 

[boki]

Thank you very much.

Boki.