how to achieve desired delay time in cmos inverter

[vead]

what should we do to achieve specific delay
just for example ( 215 ps)

I think I need following thing but its not all I am missing some
1.power supply
2.threshold voltage for nmos
3.threshold voltage for pmos
4.load capacitance

please anyone tell me what should we do to achieve 215 ps delay

 

[duke37]

I had a look at the delay of a 4001 chip, this was given as 60ns. I do not see how CMOS can get down to 215ps.

The speed of light is 300E6 m/s so you could use a short delay line and subtract one delay from another.

 

[BobK]

I had a look at the delay of a 4001 chip, this was given as 60ns. I do not see how CMOS can get down to 215ps.

The speed of light is 300E6 m/s so you could use a short delay line and subtract one delay from another.

Well, modern microprocessors are all CMOS and run at frequencies as high as 4GHz which is a 250 ps clock cycle, so they must have gate delays of well under 215 ps.

Bob

 

[vead]

can anyone explain little bit how to achieve delay time

 

[BobK]

Are you talking about in fabricating an IC or using existing CMOS logic ICs?

Bob

 

[(*steve*)]

1ps = 0.3mm at the speed of light. Let's assume half of that in coax. so 215ps will require a piece of coax 32.25mm in length.

 

[vead]

cmos lo

Are you talking about in fabricating an IC or using existing CMOS logic ICs?

Bob

CMOS logic ICs?

 

[BobK]

Bob: Why do you answer a question with a question?
vead: Why not?

Bob

 

[(*steve*)]

To do this with a CMOS Logic IC, you buy a hex inverter and a piece of wire 60mm in length.

You then discard the CMOS logic IC and connect the wire between the two points, trimming it to achieve the desired delay.

 

[BobK]

Except that it wont be inverted.

I think he is asking not asking about using existing logic chips, but rather about design logic chips that would have that gate delay.

Bob

 

[(*steve*)]

The signal becomes inverted by altering the definition of a logic 1 and 0 at both ends of the wire. The use of inverted logic at one end solves that problem very neatly.

 

[vead]

suppose we are designer and our inverter circuit need 215 ps delay time

If I know following thing then can I achieve desired delay time
1.power supply
2.threshold voltage for nmos
3.threshold voltage for pmos
4.load capacitance

how to think and what should we know to achieve 215 ps delay as designer?

 

[BobK]

suppose we are designer

This is where I am having a problem.

Bob

 

[JimW]

You can never build a chip that will have 215 ps propagation delay (unless it is a coincidence). The prop delay will change over time, output load, temperature, supply voltage, different production runs, and probably a few more variables. As a designer, you could build (design? specify? imagine?) a chip that has a maximum propagation delay of 215ps. And that max delay would have to be specified into a certain capacitive and resistive load. Strict controls on the active high and low thresholds would be key, I would think. That and output drive parameters. Having gates internal to a chip with that short a delay is reasonable. But a packaged inverter with that kind of speed? A whole lot tougher. Consider ECL instead of CMOS.

Never built a production chip, just used the fast ones, so any specifics are beyond me.

JimW

 

[vead]

You can never build a chip that will have 215 ps propagation delay (unless it is a coincidence). The prop delay will change over time, output load, temperature, supply voltage, different production runs, and probably a few more variables. As a designer, you could build (design? specify? imagine?) a chip that has a maximum propagation delay of 215ps. And that max delay would have to be specified into a certain capacitive and resistive load. Strict controls on the active high and low thresholds would be key, I would think. That and output drive parameters. Having gates internal to a chip with that short a delay is reasonable. But a packaged inverter with that kind of speed? A whole lot tougher. Consider ECL instead of CMOS.

Never built a production chip, just used the fast ones, so any specifics are beyond me.

JimW

I am not going to design real chip. I just want to learn method, how does chip design
I have made temporary specification for inverter If you want to see I can post here