Help with a logic LED testing circuit 4049 IC question.

[apples]

So I am working my way through some stuff. Making the circuit on this website here. http://www.play-hookey.com/digital/experiments/logic_indicators.html

But there is no circuit diagram so it is a little bit confusing to me. I have made up what I think it the correct circuit for this project, but would like some one to check it for me and explain where my negative wire goes?

1. the 4049 is powered by my 5v regulated supply.
2. the input of a 4049 can be up to 15V.
3. So I figure the + of the (up to 15v signal) goes on any one of the 6 inputs.
4. Where does the negative of that test signal go? Just on the same negative rail as the negative rail that is for the IC as well?

I have included a drawing.

I think I am right, but not sure.

Peter

 

[(*steve*)]

You're showing the 15V signal shorted.

With a 5V rail, no signal should normally exceed -0.7 to 5.7V (But yeah, these devices allow 15V on any input)

Some of your inputs appear to be floating (you should tie them to gnd or Vdd (no need for a resistor).

I expect that the input signal should go between the ground and one of the inputs on pins 3, 5, and 7.

 

[apples]

You're showing the 15V signal shorted.
Okay but shouldn't the positive lead/probe/clip go onto either of the input pins 3,5 or 7?


With a 5V rail, no signal should normally exceed -0.7 to 5.7V (But yeah, these devices allow 15V on any input)
You just saying this as a heads up right? I think this circuit is so that you can take a higher logic level signal and bring it back down to the standard 5v level. What is the true definition of a logic signal, is it meant to be that -0.7 to 5.7v? I did read some where they have "high " logic levels where this CMOS IC is an example of how it can be used to brind it down to the standard logic voltages.

Some of your inputs appear to be floating (you should tie them to gnd or Vdd (no need for a resistor).
Yeah just did not draw them in. I knew someone would say this.

I expect that the input signal should go between the ground and one of the inputs on pins 3, 5, and 7.
But this is what I did, I put my +ve to the Input 1 (pin3), but where does that loose end of the -ve wire go then, if you say that I have it shorted?

 

[KrisBlueNZ]

I put my +ve to the Input 1 (pin3), but where does that loose end of the -ve wire go then, if you say that I have it shorted?

Like you said, the negative side of your input voltage goes to the common ground rail, VSS, the negative side of your 5V supply.

You have the input voltage shorted out because your diagram shows the +ve side of the input voltage connecting to the bottom end of the resistor, which is grounded, instead of the top end of the resistor, which connects to the input pin on the 4049. I don't think you meant to draw it that way.

 

[(*steve*)]

You're showing the 15V signal shorted.
Okay but shouldn't the positive lead/probe/clip go onto either of the input pins 3,5 or 7?

Yes, but you show it as going to the wrong end of the resistor.

With a 5V rail, no signal should normally exceed -0.7 to 5.7V (But yeah, these devices allow 15V on any input)

You just saying this as a heads up right? I think this circuit is so that you can take a higher logic level signal and bring it back down to the standard 5v level. What is the true definition of a logic signal, is it meant to be that -0.7 to 5.7v? I did read some where they have "high " logic levels where this CMOS IC is an example of how it can be used to brind it down to the standard logic voltages.

Yeah, just a heads up. This device doesn't "bring it back to 5V" it just handles voltages greater than 5V without breaking into a sweat.

Some of your inputs appear to be floating (you should tie them to gnd or Vdd (no need for a resistor).

Yeah just did not draw them in. I knew someone would say this.

I expect that the input signal should go between the ground and one of the inputs on pins 3, 5, and 7.

But this is what I did, I put my +ve to the Input 1 (pin3), but where does that loose end of the -ve wire go then, if you say that I have it shorted?

I noted this above. There is a resistor between the place you show the connection being made and any of the pins I mentioned.

 

[apples]

Okay thanks for clearing that up guys.

 

[(*steve*)]

What is the true definition of a logic signal

Sorry, I didn't answer this.

The short answer is that it's dependant on the logic family.

The long story involves specifications of the minimum acceptable output high voltage, the maximum acceptable output low voltage, and corresponding values for the input voltages.

The input voltages have more freedom to allow fan-out and loading, etc.

This is typically only a concern when you're in very noisy environments or when you're interfacing different types of logic together (or interfacing analog and digital)

 

[gorgon]

1. the 4049 is powered by my 5v regulated supply.
2. the input of a 4049 can be up to 15V.
3. So I figure the + of the (up to 15v signal) goes on any one of the 6 inputs.

You should be aware that the input of a general 4049B circuit can NOT be more than Vdd+0.5V as a rule.

The 15V input limit is exclusively for the HEF4049B chip. So you need to get an identical designated circuit to do what you describe.

Overvoltage on inputs without a limiter is not good design practice.

OK, I yield and 'remove' my comment after looking through a number of different datasheets.
@Steve: You are correct in your comment.
However since I found the voltage limitation in a datasheet last night, there may be differences between the brands, and any such use should be done after checking the datasheet for that particular component.

TOK

 

[(*steve*)]

I think it's a feature of the 4049. For example the CD4049 datasheet says:

CD4049UBC • CD4050BC
Hex Inverting Buffer •
Hex Non-Inverting Buffer
General Description
The CD4049UBC and CD4050BC hex buffers are monolithic
complementary MOS (CMOS) integrated circuits constructed
with N- and P-channel enhancement mode
transistors. These devices feature logic level conversion
using only one supply voltage (VDD). The input signal high
level (VIH) can exceed the VDD supply voltage when these
devices are used for logic level conversions. These
devices are intended for use as hex buffers, CMOS to DTL/
TTL converters, or as CMOS current drivers, and at VDD =
5.0V, they can drive directly two DTL/TTL loads over the
full operating temperature range.

(my bolding)

 

[Harald Kapp]

The CD4049B's datasheet states under "features":
- Special input protection permits input voltages greater than VDD

Look at the schematics on page 2. This IC doesn't have the standard input protection where a diode each go from in to Vdd and to GND. Instead there is a 30 V zener diode from in to GND, thus allowing input voltages > Vdd.

 

[gorgon]

The CD4049B's datasheet states under "features":
- Special input protection permits input voltages greater than VDD

Look at the schematics on page 2. This IC doesn't have the standard input protection where a diode each go from in to Vdd and to GND. Instead there is a 30 V zener diode from in to GND, thus allowing input voltages > Vdd.

Yes, I've edited my response. There are small differencies from brand to brand, I've seen limits as low as 13V on some.

Still, the logic levels will still be inside the Vdd envelope as normal, with a switching point around Vdd/2.

TOK