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Help with 4510 bidirectional visitor counter
- Thread starter Limerickr
- Start date
Arouse1973
Adam
Vss of U2 is connected to the reset pin of U1, is this correct? Also what are you doing with PE, I can't see this on your circuit. What is all the fancy logic gates on the input for.
Adam
Adam
KrisBlueNZ
Sadly passed away in 2015
That schematic is poorly drawn. I've highlighted some obvious issues I noticed.
The path I've marked with red lines may not be wrong, but the way it has been drawn makes me suspect that the diagram hasn't been checked very carefully and that makes me suspect it has other "real" errors. The connections I've marked with red ovals are at least missing connection dots, and look like they could be wrong as well.
All of the gate ICs have different circuit references - the four NAND gates are marked U10A, U11A, U12A and U13A, instead of U10A~D. This is another clue that the schematic has issues. In other words, I have little confidence in that diagram. Can you fix it up and re-post it please. Also, the pin functions are barely readable and there are no pin numbers on the ICs. If you only have a printout of it, just make the corrections using a pen and white-out.
U8A is not needed. A signal that's the opposite of U13A's output is already available on U12A's output, and you can use that instead of wasting an inverter.
If you've connected your components so they should work, ignoring the diagram, a possible problem is a race condition between the outputs of U6A and U8A. The counters are clocked from U6A and the up/down inputs are fed from U8A. The counter requires that the up/down input is stable for a certain minimum length of time (called the setup time) before the active edge on the clock signal. If both signals change at exactly, or almost exactly, the same time, the behaviour of the counter is not defined. Look at the timing diagrams in the data sheet and Google setup and hold times, and race condition, for more information.
I haven't checked the connections to the counters because I suspect there are errors in the schematic and because the pin functions are barely readable.
P.S. Welcome to Electronics Point
The path I've marked with red lines may not be wrong, but the way it has been drawn makes me suspect that the diagram hasn't been checked very carefully and that makes me suspect it has other "real" errors. The connections I've marked with red ovals are at least missing connection dots, and look like they could be wrong as well.
All of the gate ICs have different circuit references - the four NAND gates are marked U10A, U11A, U12A and U13A, instead of U10A~D. This is another clue that the schematic has issues. In other words, I have little confidence in that diagram. Can you fix it up and re-post it please. Also, the pin functions are barely readable and there are no pin numbers on the ICs. If you only have a printout of it, just make the corrections using a pen and white-out.
U8A is not needed. A signal that's the opposite of U13A's output is already available on U12A's output, and you can use that instead of wasting an inverter.
If you've connected your components so they should work, ignoring the diagram, a possible problem is a race condition between the outputs of U6A and U8A. The counters are clocked from U6A and the up/down inputs are fed from U8A. The counter requires that the up/down input is stable for a certain minimum length of time (called the setup time) before the active edge on the clock signal. If both signals change at exactly, or almost exactly, the same time, the behaviour of the counter is not defined. Look at the timing diagrams in the data sheet and Google setup and hold times, and race condition, for more information.
I haven't checked the connections to the counters because I suspect there are errors in the schematic and because the pin functions are barely readable.
P.S. Welcome to Electronics Point
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