db said:
I am working on a hobbyist project that requires a switching
regulator. I have a pretty good math background and have spent the last three
weeks studying control and feedback theory and working through some
exercises.
I am trying to derive a response curve that matches a response
curve(Figure 8) given in the datasheet for the LT1765 switching
regulator. I am using a model given in Figure 7 of the data sheet.
My biggest question is regarding the term "overall loop response".
What does this mean exactly. Is this closed loop, open loop,
disturbance response? Maybe it is marketing fluff.
The closest match I have found is when I use P/(1+PC) which I have
seen referred to as the load disturbance sensitivity function. Still the
magnitudes and phases do not match what I see in the datasheet.
Overall Loop Response is probably the Open Loop Response, the combined power
circuit, output filter, feedback divider and amplifier gains, the control to
output transfer function with the loop open. Closed Loop Response is the
control to output transfer function with the loop closed. Loop Response is
the difference between the two.
I'm not sure where your P/(1+PC) comes from, not too clever you see.
However, it looks like you may be using it as a 'fudge factor' to make your
results agree with the data sheet. One thing you may have missed in your
sums is the effect of the voltage divider between the output of the supply
and the input to the error amplifier.
This IC uses a transconductance error amplifier with no overall feedback
from its output to its input.
If it was a 'normal' error amplifier with the gain setting components
applied from output to input to tailor its response then R2 is ignored. The
overall response of the error amplifier is set by R1 and the feedback
network. R2 doesn't enter into things.
In this case there is no feedback from the output to the input of the error
amplifier and R1 and R2 become part of your transfer function as an
attenuator. VOUT/VIN = R2/(R1 + R2), notice R2 is now important.
Perhaps this is what's missing from your sums. Even so it will not affect
the overall shapes of the curves. All you will see is a relative overall
shift in the amplitude response. The phase response will remain the same.
LT don't do a very good job of explaining the compensation in this
application note. They blurts some sums and then 'et voila'.... figure 8).
They also miss out some relevant information that would make your job easier
and more meaningful. Improve the confidence factor so to speak.
The IC implements slope compensation to avoid subharmonic oscillation but
the big question is wether it is optimised for your particular application.
Now I would initially suggest it isn't, however.....
Assuming the slope compensation is optimised then for a peak current mode
control loop operating with continuous inductor current the current loop
crossover frequency is Fs/2.pi.D.
The D part is taken care of by the inductor value and step down ratio which
then fixes the amount of slope compensation applied. Once the sums are done
and applied then the crossover frequency is fixed, afterwards it doesn't
really vary with D.....
With the current loop closed its response is flat up to this frequency and,
ideally, then assumes a first order roll off. Below this frequency the phase
is 0 at this frequency it is -45 and then approaches -90 above this
frequency. This ignores the effect of that current amplifier. If its gain
bandwidth product is too low then its transfer function will upset those
figures. In this case with a 1.26MHz switcher and a gain of 40 the GBW of
the amplifier has to be in excess of 50MHz......
Now, LT are the analog Gurus and they apply their slope compensation after
this amplifier. Do we believe they are that good? Without asking them just
put your faith in LT and believe. The remaining question is wether that
slope compensation is optimised for your particular application. There is
nothing in the sums that suggests it is but they do have a patent pending on
some do-hicky that might sort it out for you????
You place your voltage loop around this and have to pick its crossover
frequency. If you want to avoid the additional gain and phase bits in the
current loop then being safe you might guess that the current loop really
crosses over at Fs/2.pi and pick a voltage loop crossover of half of this.
That's about 100KHz and becomes your 'God' point. Figure 8) seems to achieve
30KHz so you might choose that instead. I'm just giving an example and,
because I'm not really doing it, I'm going to act hard.
Either way, as I say, that frequency becomes your 'God' point.
Now, hand on heart with no provisos, this is how you do it.
First off. Ignore what the load is. Chances are you don't know what the load
is and it isn't going to be a pure resistor and will probably only affect
the low frequency response and improve things later on. It just confuses the
issue and you might/can/will check things later.
Next, ignore the capacitor ESR. Now that seems dodgy because it is going to
be important. Once again though it's just too much too soon. You're going to
make it go away later so for the moment ignore it. If you worry about it now
things will just end up bent.
Here we go.
You have your internal current loop with a transconductance of 5A/V
[1/(0R005 x 40)] driving your output filter capacitor. A current source
driving a capacitor gives a first order system. I call it a DC pole. The
response is -20dB/DEC with a constant -90 phase shift. It hits 0dB, or 1V/V
when the capacitor has an impedance of 1/gm or in this case 1/5 or 0R2.
Taking the example of a 100uF capacitor that happens at 1/2.pi.R.C or about
8KHz.
Next you add in that voltage divider that sets the output voltage. Let's say
you want 2V4 out with a 1V2 reference, because its easy. Ignoring the
required amplifier bias current.... In figure 7) you end up with R1=R2. The
gain is R2/(R1+R2) or 0.5. That drops your 0dB point to 4KHz. The system is
still first order.
You want a crossover frequency of 100KHz so the gain needed from the error
amplifier is 100KHz/4KHz or 25. Its gm is 850uA/V so you need a load
resistor, ignoring the 500K that's already there, of 25/850u or about 30K.
Bung one in as RC. The system is still first order but now the 0dB,
crossover, point is 100KHz.
What you get is something that starts off huge at DC and rolls off
at -20dB/DEC with a constant -90 phase, or 90 phase lag (I'm not writing
degrees here) and hits 0dB at 100KHz. The phase margin is +90 and it's
eminently stable, but... underdamped.
Let's race ahead and add CC. That puts another of these DC poles in the
response by breaking the path between RC and ground. It increases the gain
at low frequencies improving the precision and transient response. It's
called a pole zero network.
If you place the zero at half the crossover fequency, 50KHz Vs 100KHz, then
at crossover the phase lag is -135 with a phase margin of 45. This
supposedly represents a critically damped system. It overshoots and recovers
in the minimum possible time.
Sounds like a good thing, but it aint necessarily so.
With RC set to 30K and a zero frequency of 50KHz CC is 100pF.
Now the system second order from DC with a -40dB/DEC amplitude response
and -180 phase lag, 0 phase margin, up to 50KHz.. At that point the system
goes back to a first order one with -20dB/DEC and the phase lag ultimately
returns to 90 degrees with -135 at crossover or 45 phase margin.
Time to deal with the output capacitor ESR zero. Basically you get rid of it
by introducing a pole in the system at the same frequency. At this point
things seriously get away from what the folks at LT suggest. Either you
believe me or you believe them.
In figure 7) CF is used to reduce 'noise' in the system. Actually the
argument is based around the ripple contribution through the error amplifier
that could and would upset the slope compensation later on. That's valid and
whilst it does perform the function they suggest I'm using it for something
else..... to cancel the output capacitor ESR zero.
You get two choices as to where to put it. Either you use the location in
figure 7) or you stick it across R2. Now, If the required pole frequency is
close to or below the zero frequency set by RC/CC (and most times it will
be) it becomes dominant and just messes up that side of things so you place
it across R2 to separate them.
As an aside that places it on the input to the amplifier so it reduces
system noise prior to it getting into the amplifier so it doesn't have to
deal with it. Assuming your layout is 'tight'.
Back to the example of the 100uF filter capacitor. In this case it has an
ESR of 0R1 which places the zero at about 16KHz. Important bit is that CF,
at its new location across R2 sees R1 and R2 in parallel. In order to place
the pole at the right frequency you use that parallel resistance. With a
recommended value of R2 as 10K R1 is also 10K (ignoring input bias current
of the amplifier) for our 2V4 output giving a parallel resistance of 5K
which makes CF 2nF.
And that is basically...... job done. Hope it worked for you?
In the mean time.... You might like to worry about how the load resistance
and the 500K resistor affect things. In both cases, assuming pure
resistances, they reduce the system order at DC out to some pole frequency
by a factor of one and improve your phase margin at crossover.
And the 'Ain't Necessarily So' is down to an overall first order system. It
is always gauranteed to be stable, fingers crossed.
If your system response includes some second order sections then that makes
it 'conditionally stable'. If, for some reason; the system gain decides to
take a tumble; things become discontinuous, at start up, or there is some
fault you end up with 0 phase margin and it doesn't recover.
You sacrifice transient response and DC precision but you also lose the
overshoot. Just use RC to ground with CF across R2 and see if it does the
job.
There is, of course, more than one way to skin a cat. Somewhere else on the
planet the boil them alive first. Bastuds. What you can also do is.....
Your 5A/V current loop drives the output filter capacitor with its ESR. If
the ESR zero is below your intended crossover frequency then multiply that
5A/V by the ESR to get the gain. It's flat above the ESR zero. Taking that
100uF/0R1 example the ESR zero occurs at 16KHz. Above 16KHz the gain is 5A/V
x 0R1 or 0.5.
Add in the attenuation by the R1/R2 divider, call it another 0.5 which takes
you down to 0.25. If you target a crossover frequency of 100KHz then the
amplifier needs a gain of 4 at that frequency. CC, with RC shorted, needs an
impedance of 4/850u at that frequency.... so that makes CC 330pF.
Another job done....quick and dirty. However, this time the system is second
order up to 16KHz and first order beyond so the transient response, whilst
nicer, might not be so good.
DNA
Right, that's four shitloads of beer drunk with a start of the next. I'll
shut up now.
