Perhaps I don't understand, then...
The OP said he was using MOSFETs. The pictures I linked to with two MOSFET gates are NOR gates using "NMOS logic circuitry". The picture jackorocko linked to has a caption describing it as using CMOS logic. I figured the OP should try using the diagrams I linked to using only two gates instead of four. If he doesn't want to, that's fine.
The picture jackorocko linked to has the p-channel MOSFETs on the top in series, and the n-channel MOSFETs on the bottom in parallel, at least according to this diagram here:
http://en.wikipedia.org/wiki/MOSFET#Circuit_symbols
The symbols you have used in your simulation are backwards from what you describe you did. I am new to transistors, so I can't tell you why an NPN BJT has the arrow pointing out, but the n-channel MOSFET has the arrow pointing in. But from the diagram, it looks like that's the way the cookie crumbles.