half bridge drive oscillatory gate

[legg]

In a mosfet half bridge, the on-coming switch Vds is held at the
supply potential while reverse recovery current flows in the
free-wheeling arrm's diode. There's nothing to stop gate voltage from
exceeding the turn-on threshold by some volts as only Ciss is active.

When freewheeling Trr ends, The mosfet is already gate-enhanced to
exceed the peak Irr. This may equal or exceed the inductive load
current. The resulting dv/dt brings Crss into the act, but not in the
tame manner of resistive load current. The gate voltage may actually
be driven below a threshold of equilibrium by dv/dt induced gate
currents, producing oscillatory behavior.

This appears to be agravated by buffered pull-down in the drive, even
with a high impedance gate drive source.

Any advice on beating this? reduce the effectiveness of the pull-down
buffer?

RL

 

[James Arthur]

In a mosfet half bridge, the on-coming switch Vds is held at the
supply potential while reverse recovery current flows in the
free-wheeling arrm's diode. There's nothing to stop gate voltage from
exceeding the turn-on threshold by some volts as only Ciss is active.

When freewheeling Trr ends, The mosfet is already gate-enhanced to
exceed the peak Irr. This may equal or exceed the inductive load
current. The resulting dv/dt brings Crss into the act, but not in the
tame manner of resistive load current. The gate voltage may actually
be driven below a threshold of equilibrium by dv/dt induced gate
currents, producing oscillatory behavior.

This appears to be agravated by buffered pull-down in the drive, even
with a high impedance gate drive source.

Any advice on beating this? reduce the effectiveness of the pull-down
buffer?

RL

Your question isn't clear. There are two FETs, same or different
polarities, at least four diodes that could free-wheel (body+clamping
diodes), and many combinations and connections possible.

Might you mean this:

.. Vdd
.. -+-
.. |
.. +-----.
.. Q1 | |
.. ||--'-. | ^
.. ||<-. ^ - | =======
.. __||--+-' ^ | i.1 .-.-.-. load
.. | D1| \____ | | | |
.. +-----+------->>---' '--.
.. Q2 | | |
.. ||--'-. | ===
.. ||<-. ^ -
.. __||--+-' ^ D2
.. | |
.. +-----'
.. |
.. ===

where the load is flying back through D1, and Q2 is just being
driven on?

If so, I don't understand:

There's nothing to stop gate voltage from
exceeding the turn-on threshold by some volts as only Ciss is active.

The gate driver prevents it!

Cheers,
James Arthur

 

[legg]

Your question isn't clear. There are two FETs, same or different
polarities, at least four diodes that could free-wheel (body+clamping
diodes), and many combinations and connections possible.

Might you mean this:

.. Vdd
.. -+-
.. |
.. +-----.
.. Q1 | |
.. ||--'-. | ^
.. ||<-. ^ - | =======
.. __||--+-' ^ | i.1 .-.-.-. load
.. | D1| \____ | | | |
.. +-----+------->>---' '--.
.. Q2 | | |
.. ||--'-. | ===
.. ||<-. ^ -
.. __||--+-' ^ D2
.. | |
.. +-----'
.. |
.. ===

where the load is flying back through D1, and Q2 is just being
driven on?
Yes


If so, I don't understand:


The gate driver prevents it!

The gate threshold is exceeded without the effects of Crss during
reverse recovery. When Crss begins to affect the gate, it does so
severely enough to turn off the fet temorarily, initiating
oscillation.

That's the interesting thing. The gate drive is fairly high impedance,
though assisted at the gate with pnp active pull-down.

The oscillation of interest is 4MHz, , source current with slow' rise
fast reduction, with peaks exceeding the inductive load current by a
factor of ~2.

The oscillation can be sustained for many microseconds, and the
resulting EMI confuses nearby electronics. Very lossy and heading
towards valhalla, if not disabled promptly, by a reduction of load.

RL

 

[James Arthur]

. Vdd
. -+-
. |
. +-----.
. Q1 | |
. ||--'-. | ^
. ||<-. ^ - | =======
. __||--+-' ^ | i.1 .-.-.-. load
. | D1| \____ | | | |
. +-----+------->>---' '--.
. Q2 | | |
. ||--'-. | ===
. ||<-. ^ -
. __||--+-' ^ D2
. | |
. +-----'
. |
. ===





The gate threshold is exceeded without the effects of Crss during
reverse recovery.

Okay, that's because you're driving Q2 'on', right?

When Crss begins to affect the gate, it does so
severely enough to turn off the fet temorarily, initiating
oscillation.

Then the drive isn't stiff enough. You need a heftier driver, one
that can overcome the Miller capacitance * dV/dt.

If it oscillates even with a stiff driver then the problem is likely
parasitics and you need damping: a small gate resistor or a ferrite
bead. That's not your problem though.

That's the interesting thing. The gate drive is fairly high impedance,
though assisted at the gate with pnp active pull-down.
Exactly.

The oscillation of interest is 4MHz, , source current with slow' rise
fast reduction, with peaks exceeding the inductive load current by a
factor of ~2.

Best,
James Arthur

 

[Fred Bloggs]

The oscillation of interest is 4MHz, , source current with slow' rise
fast reduction, with peaks exceeding the inductive load current by a
factor of ~2.

That's your problem: you do not have enough channel enhancement margin
at the instant of diode recovery and the FET is going high gain linear.
The nonlinear diode reverse recovery I-V and a bunch of phase delays
equate to oscillation. A possible fix is to reduce the high frequency
linear gain with an R+C snubber from the load to GND.

 

[legg]

On 27 Apr 2007 17:32:41 -0700, James Arthur <[email protected]>
wrote:

Okay, that's because you're driving Q2 'on', right?


Then the drive isn't stiff enough. You need a heftier driver, one
that can overcome the Miller capacitance * dV/dt.

If it oscillates even with a stiff driver then the problem is likely
parasitics and you need damping: a small gate resistor or a ferrite
bead. That's not your problem though.

The gate drive is already a combination of the two techniques you
recommend. As the reverse recovery of the freewheeling diode/fet has
to be handled, fast turn on with a stiff driver is not an option in
the bridge. The low impedance turn-off provides stiff drive, when
permitted.

Exactly.

Yes..... exactly the problem.
If gate drive modifications are the only option, then degrading the
turn-off circuit is one logical step, with efficiency implications of
it's own.

RL

 

[legg]

That's your problem: you do not have enough channel enhancement margin
at the instant of diode recovery and the FET is going high gain linear.
The nonlinear diode reverse recovery I-V and a bunch of phase delays
equate to oscillation. A possible fix is to reduce the high frequency
linear gain with an R+C snubber from the load to GND.

Probably agravated by the upper mosfet's reciprocating the behavior.

Isn't turn on, accompanied by stable gate waveform threshold plateaus
also 'linear'?

An original functional circuit using STW18NB40 had performance that
was only degraded at higher power levels by the introduction of
assisted turn-off.

Substituting IRFP360LC into the modified circuit produced the
oscillations, at very modest power levels, although the physical
characteristics of the devices are very similar.

Two backwards steps.

Output snubbing, at 47pF, is probably only symbolic at present. In
high voltage circuits, snubbers are easy ways to throw away power, but
I can probably double it. Compared to Coss of >400pF, it's a
flea-bite.

RL

 

[James Arthur]

On 27 Apr 2007 17:32:41 -0700, James Arthur <[email protected]>
wrote:






The gate drive is already a combination of the two techniques you
recommend.

But I understood the followin passage to mean the gate was only
pulled _down_ hard, but not so when driven high:

If the gate is not driven hard 'high,' then why not? Normally, it
should be.

It sounds like your driver is instead gently goosing the FET into its
linear region, and the FET, possessing a reactive load, proceeds to
oscillate.

As the reverse recovery of the freewheeling diode/fet has
to be handled, fast turn on with a stiff driver is not an option in
the bridge.

Why? The standard approach is to just brute-force rip the charge
out of that freewheeling diode, i.e., damn the torpedoes, turn Q2 on
hard and fast. That's why gate driver ICs put out _amps_--to rapidly
traverse the danger zone, avoiding this very problem.

How fast are you switching anyhow? You haven't mentioned any
numbers. How do we know irr is a problem?

If you can't abide shoot-through currents, a ferrite bead on
Q2(drain) would allow quick transitions despite D1.

The low impedance turn-off provides stiff drive, when
permitted.

Really, you have two kinds of options: to keep the FET from getting
and staying linear in the first place (i.e, avoid lingering in the
linear region during transitions), or to prevent it from oscillating
when it does (Fred's suggestions).

Yes..... exactly the problem.
If gate drive modifications are the only option, then degrading the
turn-off circuit is one logical step, with efficiency implications of
it's own.

That doesn't help--the load still flies back into D1, and D1
recovery still applies.

If you're worried about irr(D1), what kind of diode are you using
for D1, how much freewheeling current is it passing. and how fast are
the transitions (i.e., what are the trr requirements)? Might there be
better diode choices? These are all things to ponder.

RL

Best wishes,
James Arthur

 

[legg]

But I understood the followin passage to mean the gate was only
pulled _down_ hard, but not so when driven high:


If the gate is not driven hard 'high,' then why not? Normally, it
should be.

It sounds like your driver is instead gently goosing the FET into its
linear region, and the FET, possessing a reactive load, proceeds to
oscillate.


Why? The standard approach is to just brute-force rip the charge
out of that freewheeling diode, i.e., damn the torpedoes, turn Q2 on
hard and fast. That's why gate driver ICs put out _amps_--to rapidly
traverse the danger zone, avoiding this very problem.

How fast are you switching anyhow? You haven't mentioned any
numbers. How do we know irr is a problem?

If you can't abide shoot-through currents, a ferrite bead on
Q2(drain) would allow quick transitions despite D1.


Really, you have two kinds of options: to keep the FET from getting
and staying linear in the first place (i.e, avoid lingering in the
linear region during transitions), or to prevent it from oscillating
when it does (Fred's suggestions).


That doesn't help--the load still flies back into D1, and D1
recovery still applies.

If you're worried about irr(D1), what kind of diode are you using
for D1, how much freewheeling current is it passing. and how fast are
the transitions (i.e., what are the trr requirements)? Might there be
better diode choices? These are all things to ponder.

Thanks for the advice.

At 100KHz, >300V switching losses account for close to 3/4 of the
losses in the mosfets. As faster switching would not reduce the qrr,
this is considered a fixed loss, as irr simply increases linearly with
di/dt.

Any modest increase in fall time that resulted would be expected to
aggravate EMI, which is one of the features of this pre-existing
circuit that I have been assigned to correct. As it fits into a family
of others, both more and less complex and with more and less capacity,
the choice of options is limited by expectations concerning pricing,
volume, complexity and IP.

This is particularly the case when it comes to modifying a power train
that has been demonstrated functional in the application. The assisted
turn-off was intended only to assist in reducing dissipation in the
driver, who's body is being down-sized in a move to SMT.

The exact topology is not as straight forward as originally outlined,
but the devices involved in the oscillation refered to in the OP are
accurately represented by function during the relevant period of time.

RL.

 

[James Arthur]

Thanks for the advice.

At 100KHz, >300V switching losses account for close to 3/4 of the
losses in the mosfets. As faster switching would not reduce the qrr,
this is considered a fixed loss, as irr simply increases linearly with
di/dt.

Any modest increase in fall time that resulted would be expected to
aggravate EMI, which is one of the features of this pre-existing
circuit that I have been assigned to correct. As it fits into a family
of others, both more and less complex and with more and less capacity,
the choice of options is limited by expectations concerning pricing,
volume, complexity and IP.

This is particularly the case when it comes to modifying a power train
that has been demonstrated functional in the application. The assisted
turn-off was intended only to assist in reducing dissipation in the
driver, who's body is being down-sized in a move to SMT.

The exact topology is not as straight forward as originally outlined,
but the devices involved in the oscillation refered to in the OP are
accurately represented by function during the relevant period of time.

RL.

Ah hah, the motivation for the slow turn-on emerges: EMI. The plot
thickens...

A ferrite bead on Q2's drain then? Q2 could switch quickly
(avoiding oscillation), but at low current (and low EMI). The current
ramp-up would follow, with a slew rate controlled by the bead,
lowering EMI. Q2's switching losses would be low.


Two more comments: a) the main EMI problem could be from the
oscillation; fast switching might be okay, b) I agree the fact that
the oscillation lasts so long _does_ suggest rectification or some
other interaction within the driver (even a wimpy driver should slew
through the linear region, even if/while the FET oscillates) .

Best,
James Arthur