FTDI 245 USB chip and a comment Ian Stirling made 2 years ago.

[Cory Seligman]

HI all,

I'm working with a FTDI245BM trying to interface it to a lot of
hardware (need to nearly simulate an ISA bus with about 24 channels of
8 bit i/o) and I was googling around looking for a easy way to do
it....

And I happened upon this comment by Ian Stirling, who frequents this
group (are you listening?)

"I think I see a nice simple way to nearly trivially connect up to 32
8255s to a USB chip, for 768 IO.
Have to inspect datasheets."

So my question is this:

Did you ever manage to do it (trivially), and if you did, how?

I can see how it could be trivial with a pic uC and some glue logic in
between, but the lack of address lines on the ftdi245 has got me kinda
stumped. I can see how to fake it by, say, using 4 bits for address
and 4 bits for High/Low nybble multiplexed data, but i'd hardly call
that trivial.

any pointers?

thanks in advance (and to anyone else who replies too)

cheers,
Cory

 

[Paul Burke]

HI all,

I'm working with a FTDI245BM trying to interface it to a lot of
hardware (need to nearly simulate an ISA bus with about 24 channels of
8 bit i/o) and I was googling around looking for a easy way to do
it....

Did you ever manage to do it (trivially), and if you did, how?

I can see how it could be trivial with a pic uC and some glue logic in
between, but the lack of address lines on the ftdi245 has got me kinda
stumped.

It's as trivial as any byte-at-a-time serial system is ever going to be.
And it's never going to be anywhere near as fast as the ISA bus. Assume
you don't want DMA or interrupts, if you do tough..Just think of it as a
serial comms system, use any technique that would work with RS232, for
example header (includes R/W/IO), addr1,addr2,addr3 if memory, data...
if do it all in ASCII hex, that's 6 bytes per transaction either way,
you might get a turnround rate of 50000 transactions/sec if you are
lucky with framing delays.

Paul Burke

 

[Ian Stirling]

HI all,

I'm working with a FTDI245BM trying to interface it to a lot of
hardware (need to nearly simulate an ISA bus with about 24 channels of
8 bit i/o) and I was googling around looking for a easy way to do
it....

And I happened upon this comment by Ian Stirling, who frequents this
group (are you listening?)

"I think I see a nice simple way to nearly trivially connect up to 32
8255s to a USB chip, for 768 IO.
Have to inspect datasheets."

So my question is this:

I've forgotten the details, as I ended up not doing this.
I think the basic way was to direct alternate data bytes to a 5 bit
selector connected to the enable lines, with the remaining 3 bits connected
to the address lines of the 8255s.

This of course assumes perfect synchronisation.
The work-around I came up with was to have a misaligned "instruction"
at the start of the packet, to write a 1 to a pin that'll reset the
edge-triggered 'decoder' and get it back in sync.
This is followed by an instruction to reset it.
I think reads were done by writing a bit to a "read" address, which
means that a read request instead of a write request is generated
for every "instruction", and a byte is read into the USB chip.
A data bit sent at any time resets read mode. (it's of course reset
randomly during write mode, but that doesn't matter)

I think I got this down to about a couple of NAND chips, one dual flip-flop,
one selector, and a big pile of 8255s.

 

[Cory Seligman]

I've forgotten the details, as I ended up not doing this.
I think the basic way was to direct alternate data bytes to a 5 bit
selector connected to the enable lines, with the remaining 3 bits connected
to the address lines of the 8255s.

This of course assumes perfect synchronisation.
The work-around I came up with was to have a misaligned "instruction"
at the start of the packet, to write a 1 to a pin that'll reset the
edge-triggered 'decoder' and get it back in sync.
This is followed by an instruction to reset it.
I think reads were done by writing a bit to a "read" address, which
means that a read request instead of a write request is generated
for every "instruction", and a byte is read into the USB chip.
A data bit sent at any time resets read mode. (it's of course reset
randomly during write mode, but that doesn't matter)

I think I got this down to about a couple of NAND chips, one dual flip-flop,
one selector, and a big pile of 8255s.

Ok, thanks for the responses....

That's kind of what I had pictured anyhow, but I guess trivial is
different things to different people.

I'm thinking the best/easiest way for me is to use a small uC to sit
on the FTDI data bus and pump the data in and out for me. That way I
can also make full use of the buffer in the device.

I exaggerated a bit when i said I need to simulate an ISA bus. The
chips i'm interfacing to are designed to be plonked straight on an ISA
bus, but all they really need is two address bits, a R/-W and a CS.
Still, when I have 12 of them to talk to as well as about 8 DAC
channels, it uses a heap of address space.

I can use the uC to talk to the devices directly, and just stuff data
down the USB cable when it's available. I'm already almost doing this
anyhow, using ethernet instead of USB, and an entire PC instead of a
uC. It's kind of untidy though.

Thanks for both responses, anyhow.

cheers,
Cory